Datasheet

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SLUS589B− NOVEMBER 2003 − REVISED FEBRUARY 2005
3
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ELECTRICAL CHARACTERISTICS
temperature range, T
A
= −40_C to 85_C, V
DD
= 5.0 V, T
A
= T
J
; all parameters measured at zero power dissipation
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT SUPPLY
V
DD
Input voltage range 2.25 5.5
V
V
HGATE
High-side gate voltage V
BOOT
− V
SW
6
V
Shutdown current SS/SD = 0 V, Outputs off 0.25 0.45
I
DD
Quiescent current FB = 0.8 V 1.4 2.0
mA
I
DD
Switching current No load at HDRV/LDRV 1.5 4.0
mA
UVLO Minimum on-voltage 1.95 2.05 2.15 V
Hysteresis 80 150 220 mV
OSCILLATOR
f
OSC
Oscillator frequency
TPS40007
2.25 V ≤ V
DD
≤ 5.00 V
250 300 350
kHz
f
OSC
Oscillator frequency
TPS40009
2.25 V ≤ V
DD
≤ 5.00 V
500 600 700
kHz
V
RAMP
Ramp voltage V
PEAK
− V
VALLEY
0.80 0.93 1.07
V
Ramp valley voltage 0.24 0.31 0.44
V
PWM
Maximum duty cycle
(2)
TPS40007
FB = 0 V, V
DD
= 3.3 V
87.0% 94.0%
Maximum duty cycle
(2)
TPS40009
FB = 0 V, V
DD
= 3.3 V
83.0% 93.0%
Minimum duty cycle 0%
Minimum controllable pulse width
(1)(3)
100 150 ns
ERROR AMPLIFIER
V
FB
FB input voltage
Line, Temperature 0.690 0.700 0.711
V
V
FB
FB input voltage
T
A
= 25°C 0.693 0.700 0.707
V
I
FB
FB input bias current 30 130 nA
V
OH
High-level output voltage FB = 0 V, I
OH
= 1.0 mA 2.0 2.5
V
V
OL
Low-level output voltage FB =V
DD
, I
OL
= 0.5 mA 0.08 0.15
V
I
OH
Output source current COMP = 0.7 V, FB = GND 2 6
mA
I
OL
Output sink current COMP = 0.7 V, FB = V
DD
3 8
mA
G
BW
Gain bandwidth
(1)
5 10 MHz
A
OL
Open loop gain 55 85 dB
SHORT CIRCUIT CURRENT PROTECTION
I
SINK
ILIM sink current V
DD
= 5 V 11 15 19 µA
I
SINK
ILIM sink current V
DD
= 2.25 V 9.5 13.0 16.5 µA
V
OS
Offset voltage SW vs ILIM
(1)
2.25 V ≤ V
DD
≤ 5.00 −20 0 20 mV
V
ILIM
Input voltage range 2 VDD V
t
ON
Minimum HDRV pulse time in overcurrent V
DD
= 3.3 V 220 330 ns
SW leading edge blanking pulse in over-
current detection
(1)
100 ns
t
SS
Soft-start capacitor cycles as fault timer
(1)
6
(1)
Ensured by design. Not production tested.
(2)
Derate the maximum duty cycle by 3% for V
DD
< 3 V
(3)
Operating at PWM on-times of less than 100 ns could lead to overlap between HDRV and LDRV pulses.