Datasheet
ELECTRICAL CHARACTERISTICS
TPS3808
www.ti.com
.......................................................................................................................................................... SBVS050J – MAY 2004 – REVISED AUGUST 2008
1.7V ≤ V
DD
≤ 6.5V, R
LRESET
= 100k Ω , C
LRESET
= 50pF, over operating temperature range (T
J
= – 40 ° C to +125 ° C), unless
otherwise noted. Typical values are at T
J
= +25 ° C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
– 40 ° C < T
J
< +125 ° C 1.7 6.5
V
DD
Input supply range V
0 ° C < T
J
< +85 ° C 1.65 6.5
V
DD
= 3.3V, RESET not asserted
2.4 5.0 µ A
MR, RESET, C
T
open
I
DD
Supply current (current into V
DD
pin)
V
DD
= 6.5V, RESET not asserted
2.7 6.0 µ A
MR, RESET, C
T
open
1.3V ≤ V
DD
< 1.8V, I
OL
= 0.4mA 0.3 V
V
OL
Low-level output voltage
1.8V ≤ V
DD
≤ 6.5V, I
OL
= 1.0mA 0.4 V
Power-up reset voltage
(1)
V
OL
(max) = 0.2V, I
RESET
= 15 µ A 0.8 V
TPS3808G01 – 2.0 ± 1.0 +2.0
V
IT
≤ 3.3V – 1.5 ± 0.5 +1.5
Negative-going
V
IT
input threshold 3.3V < V
IT
≤ 5.0V – 2.0 ± 1.0 +2.0 %
accuracy
V
IT
≤ 3.3V – 40 ° C < T
J
< +85 ° C – 1.25 ± 0.5 +1.25
3.3V < V
IT
≤ 5.0V – 40 ° C < T
J
< +85 ° C – 1.5 ± 0.5 +1.5
TPS3808G01 1.5 3.0
V
HYS
Hysteresis on V
IT
pin – 40 ° C < T
J
< +85 ° C 1.0 2.0 %V
IT
Fixed versions
1.0 2.5
R
MR
MR Internal pull-up resistance 70 90 k Ω
TPS3808G01 V
SENSE
= V
IT
– 25 25 nA
Input current at
I
SENSE
SENSE pin
Fixed versions V
SENSE
= 6.5V 1.7 µ A
I
OH
RESET leakage current V
RESET
= 6.5V, RESET not asserted 300 nA
C
T
pin V
IN
= 0V to V
DD
5
Input capacitance,
C
IN
pF
any pin
Other pins V
IN
= 0V to 6.5V 5
V
IL
MR logic low input 0 0.3 V
DD
V
V
IH
MR logic high input 0.7 V
DD
V
DD
SENSE V
IH
= 1.05V
IT
, V
IL
= 0.95V
IT
20
Input pulse width
t
w
µ s
to RESET
MR V
IH
= 0.7V
DD
, V
IL
= 0.3V
DD
0.001
C
T
= Open 12 20 28 ms
C
T
= V
DD
180 300 420 ms
t
d
RESET delay time See Timing Diagram
C
T
= 100pF 0.75 1.25 1.75 ms
C
T
= 180nF 0.7 1.2 1.7 s
Propagation delay MR to RESET V
IH
= 0.7V
DD
, V
IL
= 0.3V
DD
150 ns
t
pHL
High to low level
SENSE to RESET V
IH
= 1.05V
IT
, V
IL
= 0.95V
IT
20 µ s
RESET delay
θ
JA
Thermal resistance, junction-to-ambient 290 ° C/W
(1) The lowest supply voltage (V
DD
) at which RESET becomes active. T
rise(VDD)
≥ 15 µ s/V.
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