Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - hot swap controller Multi-purpose TSSOP 14 Surface-mount

- Drain-to-Source Voltage - V

0.1

1000

- Drain-to-Source Current - A

DRAIN-TO-SOURCE CURRENT

DRAIN-TO-SOURCE VOLTAGE

1 10 100 1000

100

Programmed SOA 10 ms

10 ms

1 ms

100 ms

Operation in the gray area is limited by R

DS(on)

1 UVEN

VCC

SENSE

0.01 W

GATE

10 W

12 11

3 2 7 4

41.2 kW

8.25 kW

0.068 mF

470 kW

SENSE GATE OUT

FLT

IMON

TIMERGNDVREFPROGOV

TPS2492/93

LOGIC

OUT

LIM

= 34 W

LIM

= 5 A

Timeout = 10 ms

TPS2492

TPS2493

www.ti.com

SLUSA65C –JULY 2010–REVISED JANUARY 2013

Positive High-Voltage Power-Limiting Hotswap Controller

With Analog Current Monitor Output

Check for Samples: TPS2492 , TPS2493

FEATURES

DESCRIPTION

• 9-V to 80-V Operation

The TPS2492 and TPS2493 are easy-to-use, positive

• High-Side Drive for External N-FET

high voltage, 14-pin Hotswap Controllers that safely

• Programmable FET Power Limit

drive an external N-channel FET to control load

current. The programmable power foldback protection

• Programmable Load Current Limit

ensures that the external FET operates inside its safe

• Programmable Fault Timer

operating area (SOA) during overload conditions by

• Load Current Monitor Output

controlling of power dissipation. The programmable

current limit and fault timer ensure the supply,

• Power Good and Fault Outputs

external FET, and load are not harmed by

• Enable/UV, OV Inputs

overcurrent. Features include inrush current limiting,

• Latch or Auto Restart After Fault

controlled load turn-on, interfacing to down-stream

• EVM Available SLUU425

DC-to-DC converters, and power feed protection.

• Calculation Tool Available SLVC033

The analog current monitor output provides a signal

ready for sampling with an external A/D converter.

APPLICATIONS

Additional features include programmable overvoltage

• Server Backplanes

and undervoltage shutdown, power-good for

coordinating loads with inrush, and a fault indicator to

• Storage Area Networks (SAN)

indicate an over-current shutdown.

• Medical Systems

• Plug-in Modules

• Base Stations

Typical Application Circuit

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (32 pages)

PAGE 1
TPS2492 TPS2493 www.ti.
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TPS2492 TPS2493 SLUSA65C – JULY 2010 – REVISED JANUARY 2013 www.ti.com PRODUCT INFORMATION (1) TEMPERATURE FUNCTION Latched -40°C to 125°C (1) PACKAGE PART NUMBER TPS2492PW PW14 Retry TPS2493PW For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder on www.ti.com.
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TPS2492 TPS2493 www.ti.com SLUSA65C – JULY 2010 – REVISED JANUARY 2013 ELECTRICAL CHARACTERISTICS 9 V ≤ VVCC ≤ 80 V, -40°C ≤ TJ ≤ 125°C, VTIMER = 0 V and all outputs unloaded. Typical specification are at TJ = 25°C, VVCC = 48 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Supply Current (VCC) IVCC Enabled VUVEN = Hi, VSENSE = VOUT = VVCC 665 1000 IVCC Disabled VUVEN = Lo, VSENSE = VVCC, VOUT = 0 120 250 Rising 8.4 8.8 V 100 150 mV 7.5 20 µA 4 4.
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TPS2492 TPS2493 SLUSA65C – JULY 2010 – REVISED JANUARY 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) 9 V ≤ VVCC ≤ 80 V, -40°C ≤ TJ ≤ 125°C, VTIMER = 0 V and all outputs unloaded. Typical specification are at TJ = 25°C, VVCC = 48 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Gate Drive Output (GATE) GATE sourcing current IGATE GATE sinking current VSENSE = VVCC; V(GATE-OUT) = 7 V; VUVEN = Hi 15 22 35 VUVEN = Lo; VGATE = VVCC 1.8 2.4 2.
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TPS2492 TPS2493 www.ti.com SLUSA65C – JULY 2010 – REVISED JANUARY 2013 DEVICE INFORMATION Functional Block Diagram VCC 14 4 V REF 2 VREF 22 mA Charge Pump ENABLE 50 mV PROG 12 GATE 14 V 3 + SENSE 13 Constant Power Engine S 2 mA + 11 OUT + AV = 48 S 6 IMON 8 PG 9 FLT 4 TIMER 9-ms Deglitch + 2.7 V 1.25 V GND 7 UVLO + 8.4 V 8.3 V ENABLE 25 mA UVEN 1 + Fault Logic 1.35 V 1.25 V 1.35 V 1.26 V OV + 4V 1V 2.
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TPS2492 TPS2493 SLUSA65C – JULY 2010 – REVISED JANUARY 2013 www.ti.com PW PACKAGE (top view) UVEN 1 14 VCC VREF 2 13 SENSE PROG 3 12 GATE TIMER 4 11 OUT OV 5 10 NC IMON 6 9 FLT GND 7 8 PG TERMINAL FUNCTIONS TERMINAL 6 I/O DESCRIPTION NAME NO. UVEN 1 I A low input inhibits GATE. A logic input can drive this pin as an enable. VREF 2 O 4-V reference voltage used to set the power threshold on PROG pin.
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TPS2492 TPS2493 www.ti.com SLUSA65C – JULY 2010 – REVISED JANUARY 2013 DETAILED PIN DESCRIPTION The following description relies on the Typical Application Diagram shown on page 1, and the Functional Block Diagram. VCC: This pin is associated with three functions: 1. Biasing power to the integrated circuit, 2. Input to power on reset (POR) and under-voltage lockout (UVLO) functions, and 3. Voltage sense at one terminal of RSENSE for M1 current measurement.
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TPS2492 TPS2493 SLUSA65C – JULY 2010 – REVISED JANUARY 2013 www.ti.com VREF: Provides a 4.0-V reference voltage for use in conjunction with R4/R5 of the Typical Application Circuit to set the voltage on the PROG pin. The reference voltage is available once the internal POR and UVLO thresholds have been met. It is not designed as a supply voltage for other circuitry, therefore ensure that no more than 1 mA is drawn.
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TPS2492 TPS2493 www.ti.com SLUSA65C – JULY 2010 – REVISED JANUARY 2013 PG: The power good output is an active low, open-drain output intended to interface to downstream DC-to-DC converters or monitoring circuits. PG goes low after VDS of M1 has fallen to about 1.25 V and a 9-ms deglitch time period has elapsed. PG is open drain whenever UVEN is low, VDS of M1 is above 2.7 V, or UVLO is active. PG can also be viewed as having an output voltage monitor function.
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TPS2492 TPS2493 SLUSA65C – JULY 2010 – REVISED JANUARY 2013 www.ti.com TYPICAL CHARACTERISTICS SUPPLY CURRENT vs SUPPLY VOLTAGE CURRENT LIMIT TRIP vs SUPPLY VOLTAGE 55 900 − Current Limit Trip − mV V( VCC − Sense) TJ = 125°C 800 ICC - Supply Current - mA 700 600 500 TJ = -40°C TJ = 25°C 400 300 200 100 9 19 29 49 39 59 VCC - Supply Voltage - V 69 52 TJ = −405C 51 50 TJ = 255C 49 48 TJ = 1255C 47 46 9 79 19 29 39 49 59 VCC − Supply Voltage − V 69 Figure 1. Figure 2.
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TPS2492 TPS2493 www.ti.com SLUSA65C – JULY 2010 – REVISED JANUARY 2013 TYPICAL CHARACTERISTICS (continued) GATE PULL DOWN CURRENT vs SUPPLY VOLTAGE (UVEN = 4 V, V(VCC – SENSE) = 200 mV) CURRENT LIMIT RESPONSE TIME vs SUPPLY VOLTAGE (UVEN = 4 V, V(VCC – SENSE) = 200 mV) 215 1200 195 T − Current Limit Response Time − nS I Gate − Gate Pulldown Current − mA TJ = 1255C TJ = −405C 175 TJ = 255C 155 135 TJ = 1255C 115 95 75 9 19 29 39 49 59 VCC − Supply Voltage − V Figure 5.
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TPS2492 TPS2493 SLUSA65C – JULY 2010 – REVISED JANUARY 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) TIMER CHARGE/DISCHARGE RATIO vs SUPPLY VOLTAGE AND TEMPERATURE UVEN AND OV THRESHOLD VOLTAGE (falling) vs SUPPLY VOLTAGE 1.255 VUVEN - UVEN Threshold Voltage (Falling) - V ITimer − Charge/Discharge Ratio 9.80 9.75 TJ = 255C TJ = −405C 9.70 TJ = 1255C 9.65 TJ = 125°C 1.253 1.252 1.251 1.250 1.249 1.248 1.247 TJ = 25°C TJ = -40°C 1.246 1.245 9.
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TPS2492 TPS2493 www.ti.com SLUSA65C – JULY 2010 – REVISED JANUARY 2013 APPLICATION INFORMATION Basic Operation The TPS2492/93 features include: 1. Adjustable under-voltage and over-voltage lockout; 2. Turn-on inrush limit; 3. High-side gate drive for an external N-channel FET; 4. FET protection (power limit and current limit); 5. Adjustable overload timeout; 6. Output current monitor; 7. Status output; 8. Charge-complete indicator for downstream converter sequencing; and 9.
PAGE 14
TPS2492 TPS2493 SLUSA65C – JULY 2010 – REVISED JANUARY 2013 www.ti.com TIMER and PG Operation (Figure 13) The TIMER pin charges CT as long as limiting action continues, and discharges at a 1/10 charge rate when limiting stops. If the voltage on CT reaches 4 V before the output is charged, the external FET is turned off and either a latch-off or restart cycle commences, depending on the part type.
PAGE 15
TPS2492 TPS2493 www.ti.com SLUSA65C – JULY 2010 – REVISED JANUARY 2013 Action of the Constant Power Engine (Figure 14) The calculated power dissipated in the external FET, VDS x ID, is computed under the same startup conditions as Figure 13. The current of the external FET, labeled IIN, initially rises to the value that satisfies the constant power engine; in this case it is 25 W / 48 V = 0.52 A. The 25-W value is programmed into the engine by setting the PROG voltage using R4 and R5.
PAGE 16
TPS2492 TPS2493 SLUSA65C – JULY 2010 – REVISED JANUARY 2013 www.ti.com Response to a Hard Output Short (Figure 15, Figure 16, and Figure 17) Figure 15 shows the short circuit response over the full time-out period. An output short is applied, causing the voltage to fall, limiter action begin, and the fault timer to start. The external FET current is actively controlled by the power limiting engine and gate amplifier circuit while the TIMER pin charges CT to the 4-V threshold.
PAGE 17
TPS2492 TPS2493 www.ti.com SLUSA65C – JULY 2010 – REVISED JANUARY 2013 Figure 16.
PAGE 18
TPS2492 TPS2493 SLUSA65C – JULY 2010 – REVISED JANUARY 2013 www.ti.com The TPS2492/93 responds rapidly to a short circuit as seen in Figure 17. The falling OUT voltage is the result of the external FET and CO currents through the short circuit impedance. The internal GATE clamp causes the GATE voltage to follow the output voltage down and subsequently limits the negative VGS. The IIN waveform includes current into an input 47 µF capacitor.
PAGE 19
TPS2492 TPS2493 www.ti.com SLUSA65C – JULY 2010 – REVISED JANUARY 2013 Automatic Restart (Figure 18) The TPS2493 automatically initiates a restart after a fault has caused it to turn off the external FET. Internal control circuits use CT to count 16 cycles before re-enabling the external FET. This sequence repeats if the fault persists. TIMER has a 1:10 charge-to-discharge current ratio, and uses a 1-V lower threshold.
PAGE 20
TPS2492 TPS2493 SLUSA65C – JULY 2010 – REVISED JANUARY 2013 www.ti.com Application Design Example The following example illustrates the design and component selection process for a TPS2492/93 application. Figure 19 shows the application circuit for this design example. The requirements of this design are: • • • • • • • • • Nominal System Voltage: 12 V Maximum Operating System Voltage: 13.5 V Overvoltage Threshold: 14.5 V Undervoltage Threshold: 9.
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TPS2492 TPS2493 www.ti.com SLUSA65C – JULY 2010 – REVISED JANUARY 2013 1. Choose RSENSE Calculate RSENSE using a multiplier factor of 1.2 (20%) for VSENSE and RSENSE tolerance along with some additional margin. RSENSE = VSENSE 50mV = = 1.042mΩ 1.2 ´ ILIMIT 1.2 ´ 40A (5) Choose RSENSE = 1 mΩ, resulting in a nominal 50 A current limit. VSENSE( MAX ) ILIMIT(MAX) = RSENSE 2 LIMIT(MAX) PRSENSE = I = 55mV = 55 A 1mΩ (6) 2 ´ RSENSE = 55 A ´ 1mW = 3.
PAGE 22
TPS2492 TPS2493 SLUSA65C – JULY 2010 – REVISED JANUARY 2013 www.ti.com 3. Choose the Power Limit PLIM and the PROG Resistors, R4 and R5 M1 dissipates large amounts of power during power-up or output short circuit. Power limit, PLIM should be set to prevent the M1 die temperature from exceeding a short term maximum temperature, TJ(MAX2). Short term TJ(MAX2) may be set as high as 150°C (specified on FET datasheet) while still leaving ample margin for the typical manufacturer's rating of 175°C.
PAGE 23
TPS2492 TPS2493 www.ti.com SLUSA65C – JULY 2010 – REVISED JANUARY 2013 4. Choose the TIMER Capacitor, CT and Turn-On Time The turn on time tON, represents the time it takes the circuit to charge up the output capacitance CO and load. CT programs the fault time and should be chosen so that the fault timer does not terminate prior to completion of start up. The turn on time is a function of the type of control; current limit, power limit, or dV/dt control.
PAGE 24
TPS2492 TPS2493 SLUSA65C – JULY 2010 – REVISED JANUARY 2013 www.ti.com 5. Choose the Turn-On and Over-voltage Divider, R1 - R3 Per our system design requirements above, both over-voltage shutdown and under-voltage shutdown are desired. Equations for calculating the thresholds are: VOV _ H = VOV ´ R3 (R1+R2+R3 ) VUVEN _ H = (17) VUV ´ (R2+R3 ) (R1+R2+R3 ) (18) Assume R3 is 1 kΩ and use the following procedure to determine R1 and R2. R1+R2 = R2+R3 = R3 ´ (VOV -VOV_H ) 1k W ´ (14.5V - 1.
PAGE 25
TPS2492 TPS2493 www.ti.com SLUSA65C – JULY 2010 – REVISED JANUARY 2013 Additional Design Considerations Calculation Tool SLVC033 The calculation tool for the TPS2490/91, SLVC033, may be used with the TPS2492/93. For accurate results, the timer current constants need to be updated. This may be accomplished using the Excel Tools / Protection command along with the password provided in the tool (spreadsheet).
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TPS2492 TPS2493 SLUSA65C – JULY 2010 – REVISED JANUARY 2013 www.ti.com Adding External GATE-OUT Capacitance Avoid directly placing ceramic capacitors directly across M1 gate to source when bypassing for ESD or noise is desired. Add some small resistance in series with the capacitor if absolutely required. If the resistance is not present, the added phase shift may encourage high frequency oscillation of the combined input and output L-C circuits during startup conditions.
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TPS2492 TPS2493 www.ti.com SLUSA65C – JULY 2010 – REVISED JANUARY 2013 REVISION HISTORY Changes from Original (July 2010) to Revision A • Page Changed marketing status .................................................................................................................................................... 1 Changes from Revision A (#IMPLIED) to Revision B • Page Changed temperature rating from 80°C to 125°C in the product Information section to match the rest of the datasheet. .............
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.