Datasheet
dV
s
dt
+
15 mA
C
gd
TPS2330
TPS2331
www.ti.com
SLVS277G –MARCH 2000–REVISED JULY 2013
Table 3. Some Available N-Channel MOSFETs
CURRENT RANGE
PART NUMBER DESCRIPTION MANUFACTURER
(A)
IRF7601 N-channel, r
DS(on)
= 0.035 Ω, 4.6 A, Micro-8 International Rectifier
MTSF3N03HDR2 N-channel, r
DS(on)
= 0.040 Ω, 4.6 A, Micro-8 ON Semiconductor
0 to 2
IRF7101 Dual N-channel, r
DS(on)
= 0.1 Ω, 2.3 A, SO-8 International Rectifier
MMSF5N02HDR2 Dual N-channel, r
DS(on)
= 0.04 Ω, 5 A, SO-8 ON Semiconductor
IRF7401 N-channel, r
DS(on)
= 0.022 Ω, 7 A, SO-8 International Rectifier
MMSF5N02HDR2 N-channel, r
DS(on)
= 0.025 Ω, 5 A, SO-8 ON Semiconductor
2 to 5
IRF7313 Dual N-channel, r
DS(on)
= 0.029 Ω, 5.2 A, SO-8 International Rectifier
SI4410 N-channel, r
DS(on)
= 0.020 Ω, 8 A, SO-8 Vishay Dale
IRLR3103 N-channel, r
DS(on)
= 0.019 Ω, 29 A, d-Pak International Rectifier
5 to 10
IRLR2703 N-channel, r
DS(on)
= 0.045 Ω, 14 A, d-Pak International Rectifier
TIMER
For most applications, a minimum capacitance of 50 pF is recommended to prevent false triggering. This
capacitor should be connected between TIMER and ground. The presence of an overcurrent condition on of the
TPS2330/31 causes a 50-μA current source to begin charging this capacitor. If the overcurrent condition persists
until the capacitor has been charged to approximately 0.5 V, the TPS2330/31 latches off the transistor and pulls
the FAULT pin low. The timer capacitor can be made as large as desired to provide additional time delay before
registering a fault condition. The time delay is approximately:
dt(sec) = C
(TIMER)
(F) × 10,000(Ω)
OUTPUT-VOLTAGE SLEW-RATE CONTROL
When enabled, the TPS2330/TPS2331 controllers supply the gate of an external MOSFET transistor with a
current of approximately 15 μA. The slew rate of the MOSFET source voltage is thus limited by the gate-to-drain
capacitance C
gd
of the external MOSFET capacitor to a value approximating:
(1)
If a slower slew rate is desired, an additional capacitance can be connected between the gate of the external
MOSFET and ground.
VREG CAPACITOR
The internal voltage regulator connected to VREG requires an external capacitor to ensure stability. A 0.1-μF or
0.22-μF ceramic capacitor is recommended.
GATE DRIVE CIRCUITRY
The TPS2330/TPS2331 includes four separate features associated with each gate-drive terminal:
• A charging current of approximately 15 μA is applied to enable the external MOSFET transistor. This current
is generated by an internal charge pump that can develop a gate-to-source potential (referenced to DISCH) of
9 V–12 V. DISCH must be connected to the external MOSFET source terminal to ensure proper operation of
this circuitry.
• A discharge current of approximately 75 μA is applied to disable the external MOSFET transistor. Once the
transistor gate voltage has dropped below approximately 1.5 V, this current is disabled and the UVLO
discharge driver is enabled instead. This feature allows the part to enter a low-current shutdown mode while
ensuring that the gate of the external MOSFET transistor remains at a low voltage.
• During a UVLO condition, the gate of the MOSFET transistor is pulled down by an internal PMOS transistor.
This transistor continues to operate even if the voltage at IN is 0 V. This circuitry also helps hold the external
MOSFET transistor off when power is suddenly applied to the system.
• During an overcurrent fault condition, the external MOSFET transistor that exhibited an overcurrent condition
is rapidly turned off by an internal pulldown circuit capable of pulling in excess of 400 mA (at 4 V) from the
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