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Buck SMPS
Boost SMPS
TPIC74100-Q1
BUCK/BOOST SWITCH-MODE REGULATOR
SLIS125 DECEMBER 2006
operating in boost mode and V
(driver)
is in the crossover window of 5.8 V to 5 V, the output regulation may
contain a higher than normal ripple and only maintain a 3% tolerance. This ripple and tolerance depends on the
loading and improves with a higher loading condition. When the device is operated with low-power mode active
(CLP = low) and high output currents (>50 mA), the buck/boost transitioning can cause a reset signal at the
RESET pin.
In buck mode, the duty cycle of transistor Q1 sets the voltage V
OUT
. The duty cycle of transistor Q1 varies 10%
to 99% depending on the input voltage, V
(driver)
. If the peak inductor current (measured by Q1) exceeds 450 mA
(typical), Q2 is turned on for this cycle (synchronized rectification). Otherwise, the current recirculates through
Q2 as a free-wheeling diode. The detection for synchronous or asynchronous mode is done cycle-by-cycle.
To avoid a cross-conduction current between Q1 and Q2, an inherent delay is incorporated when switching Q1
off and Q2 on and vice versa.
In buck mode, transistor Q3 is not required and is switched off. Transistor Q4 is switched on to reduce power
dissipation.
The switch timings for transistors Q3 and Q4 are not considered. In buck mode, the logical control of the
transistors does not change.
Figure 2. Buck/Boost Switch Mode Configuration
In boost mode, the duty cycle of transistor Q3 controls the output voltage V
OUT
. The duty cycle is internally
adjusted 5% to 85% depending on the internally sensed voltage of the output. Synchronized rectification occurs
when V
(driver)
is below 5 V.
To avoid a discharging of the buffer capacitor, a simultaneous switching on of Q3 and Q4 is not allowed. An
inherent delay is incorporated between Q3 switching off and Q4 switching on and vice versa.
In boost mode, transistor Q2 is not required and remains off. Transistor Q1 is switched on for the duration of the
boost-mode operation (serves as a supply line).
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