Datasheet

f - Frequency - Hz
0
-50
-100
0 200 400 600 800 1k 1.2k
- Output Voltage - dBV
1.4k1.6k1.8k 2k
-150
-150
-100
0
-50
V
O
- Supply Voltage - dBVV
DD
V
DD
Shown in Figure 19
C
I
= 2 µF,
C
(Bypass)
= 0.47 µF,
Inputs ac-Grounded
Gain = 1V/V
C1
Frequency
217.41 Hz
C1 - Duty
20 %
C1 High
3.598 V
C1 Pk-Pk
504 mV
Voltage - V
Ch1 100 mV/div
Ch4 10 mV/div
2 ms/div
t - Time - ms
V
DD
V
O
-100
0
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20 k50 100 200 500 1 k 2 k 5 k 10 k
f - Frequency - Hz
CMRR - Common Mode Rejection Ratio - dB
V
DD
= 2.5 V to 5 V
V
IC
= 200 mV
p-p
R
L
= 8 Ω
Gain = 1 V/V
-70
-60
-50
-40
-30
-20
-10
0
10
20
30
40
10 100 10 k 100 k 1 M 10 M
-220
-180
-140
-100
-60
-20
20
60
100
140
180
220
1 k
f - Frequency - Hz
Gain - dB
Phase - Degrees
Gain
Phase
V
DD
= 3.6 V
R
L
= 8 Ω
Gain = 1 V/V
-200
-150
-100
-50
0
50
100
150
200
100 1 k 10 k 100 k 1 M
-200
-150
-100
-50
0
50
100
150
200
f - Frequency - Hz
Gain - dB
Phase - Degrees
Gain
Phase
V
DD
= 3.6 V
R
L
= 8 Ω
10 M
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
R
L
= 8 Ω
Gain = 1 V/V
V
IC
- Common Mode Input Voltage - V
CMRR - Common Mode Rejection Ratio - dB
V
DD
= 3.6 V
V
DD
= 5 V
V
DD
= 2.5 V
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
V
DD
- Supply Voltage - V
- Supply Current - mA
I
DD
0
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
1
1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
2
V
DD
= 2.5 V
V
DD
= 3.6 V
V
DD
= 5 V
Voltage on SHUTDOWN Terminal - V
- Supply Current - mA
I
DD
0.2
0
1
2
3
4
5
6
0 0.5 1 1.5 2
C
(Bypass)
- Bypass Capacitor - µF
Start-Up Time - ms
(1)
Start-Up time is the time it takes (from a
low-to-high transition on SHUTDOWN) for the
gain of the amplifier to reach -3 dB of the final
gain.
TPA6203A1
SLOS364F – MARCH 2002 – REVISED JUNE 2008 .......................................................................................................................................................... www.ti.com
TYPICAL CHARACTERISTICS (continued)
GSM POWER SUPPLY GSM POWER SUPPLY
REJECTION REJECTION COMMON MODE REJECTION RATIO
vs vs vs
TIME FREQUENCY FREQUENCY
Figure 19. Figure 20. Figure 21.
COMMON MODE REJECTION RATIO CLOSED LOOP GAIN/PHASE OPEN LOOP GAIN/PHASE
vs vs vs
COMMON MODE INPUT VOLTAGE FREQUENCY FREQUENCY
Figure 22. Figure 23. Figure 24.
SUPPLY CURRENT SUPPLY CURRENT START-UP TIME
(1)
vs vs vs
SUPPLY VOLTAGE SHUTDOWN VOLTAGE BYPASS CAPACITOR
Figure 25. Figure 26. Figure 27.
8 Submit Documentation Feedback Copyright © 2002 – 2008, Texas Instruments Incorporated
Product Folder Link(s): TPA6203A1