Datasheet

TPA3113D2
SLOS650E –AUGUST 2009–REVISED JULY 2012 www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
UNIT
V
CC
Supply voltage AVCC, PVCC –0.3 V to 30 V
–0.3 V to V
CC
+ 0.3 V
SD, GAIN0, GAIN1, PBTL, FAULT
(2)
< 10 V/ms
V
I
Interface pin voltage
PLIMIT –0.3 V to GVDD + 0.3 V
RINN, RINP, LINN, LINP –0.3 V to 6.3 V
Continuous total power dissipation See Thermal Table Table
T
A
Operating free-air temperature range –40°C to 85°C
T
J
Operating junction temperature range
(3)
–40°C to 150°C
T
stg
Storage temperature range –65°C to 150°C
BTL: PVCC > 15 V 4.8
R
L
Minimum Load Resistance BTL: PVCC ≤ 15 V 3.2
PBTL 3.2
Human body model
(4)
(all pins) ±2 kV
ESD Electrostatic discharge
Charged-device model
(5)
(all pins) ±500 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operations of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The voltage slew rate of these pins must be restricted to no more than 10 V/ms. For higher slew rates, use a 100 kΩ resister in series
with the pins.
(3) The TPA3113D2 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must be connected
to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal protection
shutdown. See TI Technical Briefs SLMA002 for more information about using the TSSOP thermal pad.
(4) In accordance with JEDEC Standard 22, Test Method A114-B.
(5) In accordance with JEDEC Standard 22, Test Method C101-A
THERMAL INFORMATION
TPA3113D2
THERMAL METRIC
(1) (2)
UNITS
PWP (28 PINS)
θ
JA
Junction-to-ambient thermal resistance 30.3
θ
JCtop
Junction-to-case (top) thermal resistance 33.5
θ
JB
Junction-to-board thermal resistance 17.5
°C/W
ψ
JT
Junction-to-top characterization parameter 0.9
ψ
JB
Junction-to-board characterization parameter 7.2
θ
JCbot
Junction-to-case (bottom) thermal resistance 0.9
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator
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