Datasheet
32
5
27
10
25
12
PVCCR
RINP
PGNDR
AGND
AVCC
NC
MUTE
VBYP
ROUTP
LOUTP
NC
NC
BSRN
BSLN
LOUTN
ROUTN
FAULT
VREG
SHUTDOWN
AGND
NC
ROSC
BSRP
BSLP
ROUTP
ROUTN
LOUTN
LOUTP
PVCCR
Exposed
ThermalPad
RINN
NC
NC
NC
NC
PGNDR
LINP
VCLAMPR
LINN
VCLAMPL
NC
PGNDL
GAIN0
PGNDL
GAIN1
PVCCL
MSTR/SLV
PVCCL
SYNC
33
4
28
9
26
11
34
3
29
8
35
2
30
7
36
1
31
6
44
17
38
23
43
18
37
24
45
16
39
22
46
15
40
21
47
14
41
20
48
13
42
19
AVCC
AVCC
FAULT
MUTE
SHUTDOWN
BSRP
ROUTP
ROUTP
ROUTN
ROUTN
BSRN
GND
GND
PVCCR
PVCCR
PGNDR
VCLAMPR
VCLAMPL
PGNDL
PVCCL
PVCCL
GND
GND
RINN
RINP
AGND
LINP
LINN
GAIN0
GAIN1
MSTR/SLV
SYNC
GND
GND
ROSC
VREG
VBYP
AGND
BSLP
LOUTP
LOUTP
LOUTN
LOUTN
BSLN
GND
PGNDR
PGNDL
GAIN0
13 14 15 16 17 18 19 20 21 22 23 24
25
26
27
28
29
30
31
32
33
34
35
36
48 47 46 45 44 43 42 41 40 39 38 37
1
2
3
4
5
6
7
8
9
10
11
12
Exposed
ThermalPad
TPA3100D2
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SLOS469F –OCTOBER 2005–REVISED AUGUST 2010
48 PIN, QFN PACKAGE 48 PIN, HTQFP PACKAGE
(TOP VIEW) (TOP VIEW)
TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTION
QFN HTQFP
NAME
NO. NO.
Shutdown signal for IC (LOW = disabled, HIGH = operational). TTL logic
SHUTDOWN 44 44 I
levels with compliance to AVCC.
RINN 2 2 I Negative audio input for right channel. Biased at VREG/2.
RINP 3 3 I Positive audio input for right channel. Biased at VREG/2.
LINN 6 6 I Negative audio input for left channel. Biased at VREG/2.
LINP 5 5 I Positive audio input for left channel. Biased at VREG/2.
GAIN0 8 7, 8 I Gain select least significant bit. TTL logic levels with compliance to VREG.
GAIN1 9 9 I Gain select most significant bit. TTL logic levels with compliance to VREG.
1, 12, 13,
GND 24, 25, 36, Connect to the thermal pad.
37
Mute signal for quick disable/enable of outputs (HIGH = outputs high-Z,
MUTE 45 45 I
LOW = outputs enabled). TTL logic levels with compliance to AVCC.
TTL compatible output. HIGH = short-circuit fault. LOW = no fault. Only
FAULT 46 46 O
reports short-circuit faults. Thermal faults are not reported on this terminal.
BSLP 18 18 I/O Bootstrap I/O for left channel, positive high-side FET.
Power supply for left channel H-bridge, not internally connected to PVCCR
PVCCL 26, 27 26, 27
or AVCC.
LOUTP 19, 20 19, 20 O Class-D 1/2-H-bridge positive output for left channel.
PGNDL 28, 29 28, 29 Power ground for left channel H-bridge.
LOUTN 21, 22 21, 22 O Class-D 1/2-H-bridge negative output for left channel.
BSLN 23 23 I/O Bootstrap I/O for left channel, negative high-side FET.
VCLAMPL 30 30 Internally generated voltage supply for left channel bootstrap capacitor.
VCLAMPR 31 31 Internally generated voltage supply for right channel bootstrap capacitor.
BSRN 38 38 I/O Bootstrap I/O for right channel, negative high-side FET.
ROUTN 39, 40 39, 40 O Class-D 1/2-H-bridge negative output for right channel.
PGNDR 32, 33 32, 33 Power ground for right channel H-bridge.
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