TP3054.
TP3054, TP3057 ‘‘Enhanced’’ Serial Interface CODEC/Filter COMBOÉ Family General Description Features The TP3054, TP3057 family consists of m-law and A-law monolithic PCM CODEC/filters utilizing the A/D and D/A conversion architecture shown in Figure 1 , and a serial PCM interface. The devices are fabricated using National’s advanced double-poly CMOS process (microCMOS).
Block Diagram FIGURE 1 TL/H/5510 – 2 Pin Description Symbol VBB Symbol Function Negative power supply pin. VBB e b5V g 5%. GNDA Analog ground. All signals are referenced to this pin. VFRO Analog output of the receive power amplifier. VCC Positive power supply pin. VCC e a 5V g 5%. FSR Receive frame sync pulse which enables BCLKR to shift PCM data into DR. FSR is an 8 kHz pulse train. See Figures 2 and 3 for timing details. DR Receive data input.
Functional Description POWER-UP ASYNCHRONOUS OPERATION When power is first applied, power-on reset circuitry initializes the COMBO and places it into a power-down state. All non-essential circuits are deactivated and the DX and VFRO outputs are put in high impedance states. To power-up the device, a logical low level or clock must be applied to the MCLKR/PDN pin and FSX and/or FSR pulses must be present. Thus, 2 power-down control modes are available.
Functional Description (Continued) (due to encoding delay), which totals 290 ms. Any offset voltage due to the filters or comparator is cancelled by sign bit integration. TRANSMIT SECTION The transmit section input is an operational amplifier with provision for gain adjustment using two external resistors, see Figure 4 . The low noise and wide bandwidth allow gains in excess of 20 dB across the audio passband to be realized.
Absolute Maximum Ratings Voltage at any Digital Input or Output If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. VCC to GNDA VCC a 0.3V to GNDAb0.
Timing Specifications Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC e 5.0V g 5%, VBB e b5.0V g 5%; TA e 0§ C to 70§ C by correlation with 100% electrical testing at TA e 25§ C. All other limits are assured by correlation with other production tests and/or product design and characterization. All signals referenced to GNDA. Typicals specified at VCC e 5.0V, VBB e b5.0V, TA e 25§ C. All timing parameters are measured at VOH e 2.0V and VOL e 0.7V.
FIGURE 2.
FIGURE 3.
Transmission Characteristics Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC e 5.0V g 5%, VBB e b5.0V g 5%; TA e 0§ C to 70§ C by correlation with 100% electrical testing at TA e 25§ C. All other limits are assured by correlation with other production tests and/or product design and characterization. GNDA e 0V, f e 1.02 kHz, VIN e 0 dBm0, transmit input amplifier connected for unity gain non-inverting. Typicals specified at VCC e 5.0V, VBB e b 5.0V, TA e 25§ C.
Transmission Characteristics (Continued) Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC e 5.0V g 5%, VBB e b5.0V g 5%; TA e 0§ C to 70§ C by correlation with 100% electrical testing at TA e 25§ C. All other limits are assured by correlation with other production tests and/or product design and characterization. GNDA e 0V, f e 1.02 kHz, VIN e 0 dBm0, transmit input amplifier connected for unity gain non-inverting. Typicals specified at VCC e 5.0V, VBB e b5.0V, TA e 25§ C.
Transmission Characteristics (Continued) Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC e 5.0V g 5%, VBB e b5.0V g 5%; TA e 0§ C to 70§ C by correlation with 100% electrical testing at TA e 25§ C. All other limits are assured by correlation with other production tests and/or product design and characterization. GNDA e 0V, f e 1.02 kHz, VIN e 0 dBm0, transmit input amplifier connected for unity gain non-inverting. Typicals specified at VCC e 5.0V, VBB e b5.0V, TA e 25§ C.
Applications Information POWER SUPPLIES This common ground point should be decoupled to VCC and VBB with 10 mF capacitors. While the pins of the TP305X family are well protected against electrical misuse, it is recommended that the standard CMOS practice be followed, ensuring that ground is connected to the device before any other connections are made.
Applications Information (Continued) TABLE II. Attentuator Tables for Z1 e Z2 e 300X (All Values in X) dB R1 R2 R3 R4 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 20 1.7 3.5 5.2 6.9 8.5 10.4 12.1 13.8 15.5 17.3 34.4 51.3 68 84 100 115 379 143 156 168 180 190 200 210 218 233 246 26k 13k 8.7k 6.5k 5.2k 4.4k 3.7k 3.3k 2.9k 2.6l 1.3k 850 650 494 402 380 284 244 211 184 161 142 125 110 98 77 61 3.5 6.9 10.4 13.8 17.3 21.3 24.2 27.7 31.1 34.
Connection Diagrams (Continued) Plastic Chip Carrier TL/H/5510 – 7 Top View Order Number TP3057V See NS Package Number V20A 14
Physical Dimensions inches (millimeters) Cavity Dual-In-Line Package (J) Order Number TP3054J or TP3057J NS Package Number J16A Molded Small Outline Package (WM) Order Number TP3054WM or TP3057WM NS Package Number M16B 15
TP3054, TP3057 ‘‘Enhanced’’ Serial Interface CODEC/Filter COMBO Family Physical Dimensions inches (millimeters) (Continued) Molded Dual-In-Line Package (N) Order Number TP3054N or TP3057N NS Package Number N16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1.
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