Network Card User Manual

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TMS320C6472/TMS320TCI6486 DSP

Ethernet Media Access Controller (EMAC)/

Management Data Input/Output (MDIO) Module

User's Guide

Literature Number: SPRUEF8F

March 2006–Revised November 2010

Summary of content (160 pages)

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TMS320C6472/TMS320TCI6486 DSP Ethernet Media Access Controller (EMAC)/ Management Data Input/Output (MDIO) Module User's Guide Literature Number: SPRUEF8F March 2006 – Revised November 2010
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Preface ...................................................................................................................................... 10 1 Introduction ...................................................................................................................... 11 2 3 4 ............................................................................................. 11 ................................................................................................................. 11 1.
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www.ti.com ................. 86 4.12 MDIO User Access Register 0 (USERACCESS0) ................................................................ 87 4.13 MDIO User PHY Select Register 0 (USERPHYSEL0) ............................................................ 88 4.14 MDIO User Access Register 1 (USERACCESS1) ................................................................ 89 4.15 MDIO User PHY Select Register 1 (USERPHYSEL1) ............................................................
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www.ti.com ............................................................. 141 5.44 MAC Address High Bytes Register (MACADDRHI) ............................................................. 142 5.45 MAC Index Register (MACINDEX) ................................................................................. 143 5.46 Transmit Channel 0-7 DMA Head Descriptor Pointer Register (TXnHDP) ................................... 144 5.47 Receive Channel 0-7 DMA Head Descriptor Pointer Register (RXnHDP) ...............
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www.ti.com List of Figures 1 EMAC and MDIO Block Diagram ........................................................................................ 12 2 Ethernet Configuration with MII Interface 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 6 .............................................................................. Ethernet Configuration with RMII Interface .............................................................
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www.ti.com 48 Receive Teardown Register (RXTEARDOWN) ...................................................................... 100 49 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) .............................................. 101 50 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) ............................................ 102 51 Transmit Interrupt Mask Set Register (TXINTMASKSET) ..........................................................
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www.ti.com List of Tables 1 Serial Management Interface Pins ...................................................................................... 13 2 EMAC1_EN Pin Description 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 8 ............................................................................................. EMAC Clock Specifications .............................................................................................. EMAC0 Interface Selection Pins ..
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www.ti.com 47 48 49 50 51 52 53 54 55 56 ................................................ MAC End-of-Interrupt Vector Register (MACEOIVECTOR) Field Descriptions.................................. Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) Field Descriptions ........................ Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) Field Descriptions ...................... Receive Interrupt Mask Set Register (RXINTMASKSET) Field Descriptions ....................................
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Preface SPRUEF8F – March 2006 – Revised November 2010 Read This First About This Manual This document provides a functional description of the Ethernet Media Access Controller (EMAC) and Physical layer (PHY) device Management Data Input/Output (MDIO) module integrated with TMS320TCI6486/TMS320C6472 devices. Included are the features of the EMAC and MDIO modules, a discussion of their architecture and operation, how these modules connect to the outside world, and the registers descriptions for each module.
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User's Guide SPRUEF8F – March 2006 – Revised November 2010 C6472/TCI6486 EMAC/MDIO 1 Introduction This document provides a functional description of the Ethernet Media Access Controller (EMAC) and Physical layer (PHY) device Management Data Input/Output (MDIO) module integrated with TMS320TCI6486/TMS320C6472 devices.
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Introduction • 1.3 www.ti.com Single MDIO, shared by both EMAC modules. Functional Block Diagram Figure 1 shows the functional block diagram of the EMAC peripherals used in the TCI6486/C6472 device. It consists mainly of: • EMAC0 • EMAC1 • CPPI buffer manager per EMAC • EMIC per EMAC • MDIO Figure 1.
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Introduction www.ti.com The EMAC module provides an efficient interface between the TCI6486/C6472 core processor and the networked community. The EMAC supports 10Base-T (10 Mbits/sec) and 100Base-TX (100 Mbits/sec) in either half- or full-duplex mode, and 1000Base-T (1000 Mbits/sec) in full-duplex mode, with hardware flow control and quality-of-service (QOS) support. Each EMAC module has a communications port programming interface (CPPI) buffer manager to manage 8K of CPPI RAM.
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Introduction www.ti.com Table 2. EMAC1_EN Pin Description (continued) Value 1 Description EMAC1 is enabled and used. Pulls on EMAC1 I/O are disabled (except RGMII pins) and the corresponding I/O buffers are powered up except RGMII output-only pins. NOTE: RGMII buffers are HSTL buffers with no internal pulls. RGMII output only pins will always be powered down even when the module is enabled. EMAC1_EN is also software programmable through the DEVCTL register.
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EMAC Functional Architecture www.ti.com 2 EMAC Functional Architecture This section discusses the architecture and basic function of the EMAC peripheral. 2.1 Clock Control The frequencies for the transmit and receive clocks are fixed by the IEEE 802.3 specification, as shown below: • 2.5 MHz at 10 Mbps • 25 MHz at 100 Mbps • 125 MHz at 1000 Mbps All clock sources, with the exception of the EMAC peripheral bus clock, are sourced from the PLL2 controller.
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EMAC Functional Architecture 2.1.3 www.ti.com GMII Clocking The GMII interface is available only on EMAC0 and requires two clock sources generated internally, the peripheral bus clock and the RFTCLK inputs to the EMAC module. SYSCLK14 is programmed to /4 for this interface to provide a 125-MHz clock to the RFTCLK input of EMAC. The GMII interface is selected by programming MACSEL0 to 2 (010b).
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EMAC Functional Architecture www.ti.com 2.3 System-Level Connections On the TCI6486/C6472 device, EMAC0 and EMAC1 support the following different types of interfaces to physical layer devices (PHYs) or switches. Each EMAC can be configured to only one interface at any given time. EMAC0 interface is selected by programming MACSEL0 [2:0] pins (see Table 4) and EMAC1 interface is selected by programming MACSEL1 [1:0] pins (see Table 5). Table 4.
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EMAC Functional Architecture www.ti.com Table 6. MACSEL0[2:0], MACSEL1[1:0], and EMAC1_EN Decoding (continued) 2.3.
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EMAC Functional Architecture www.ti.com Table 7. EMAC and MDIO Signals for MII Interface Signal Name I/O Description MTCLK I Transmit clock (MTCLK). The transmit clock is a continuous clock that provides the timing reference for transmit operations. The MTXD and MTXEN signals are tied to this clock. The clock is generated by the PHY and is 2.5 MHz at 10-Mbps operation and 25 MHz at 100-Mbps operation. MTXD[3:0] O Transmit data (MTXD).
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EMAC Functional Architecture 2.3.2 www.ti.com Reduced Media Independent Interface (RMII) Connections Figure 3 shows a TCI6486/C6472 device with integrated EMAC and MDIO interfaced to the PHY via an RMII connection. This interface is available only in 10-Mbps and 100-Mbps modes. Figure 3.
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EMAC Functional Architecture www.ti.com Table 8. EMAC and MDIO Signals for RMII Interface (continued) Signal Name I/O Description RMRXER I Receive error (RMRXER). The receive error signal is asserted for one or more reference clock periods to indicate that an error was detected in the received frame. This is meaningful only during data reception when RMCRSDV is active. It is driven synchronously to the RMII reference clock. MDCLK O Management data clock (MDCLK).
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EMAC Functional Architecture www.ti.com Table 9. EMAC and MDIO Signals for GMII Interface Signal Name I/O Description MTCLK I Transmit clock (MTCLK). The transmit clock is a continuous clock that provides the timing reference for transmit operations in 10/100 Mbps mode. The MTXD and MTXEN signals are tied to this clock when in 10/100 Mbps mode. The clock is generated by the PHY and is 2.5 MHz at 10-Mbps operation, and 25 MHz at 100-Mbps operation.
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EMAC Functional Architecture www.ti.com Figure 5. Ethernet Configuration with RGMII Interface RGTXC RGTXD[3−0] 2.5 MHz 25 MHz, or 125 MHz RGTXCTL EMAC RGREFCLK System core RGRXC RGRXD[3−0] Physical layer device (PHY) RGRXCTL Transformer RJ−45 MDIO RGMDCLK RGMDIO The RGMII interface is a reduced pin alternative to the GMII interface. The data paths are reduced, control signals are multiplexed together, and both edges of the clock are used.
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EMAC Functional Architecture www.ti.com Table 10. EMAC and MDIO Signals for RGMII Interface (continued) Signal Name I/O Description RGRXCTL I Receive control (RGRXCTL). The receive control data has the receive data valid (MRXDV) signal on the rising edge of the receive clock, and a derivative of receive data valid and receive error (MRXER) on the falling edge of RGRXC.
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EMAC Functional Architecture www.ti.com 2.3.5 Source Synchronous Serial Media Independent Interface (S3MII) Connections Figure 6 shows a TCI6486/C6472 device with an integrated EMAC and MDIO interface via S3MII connections connected to a PHY. The S3MII interface supports source synchronous 10-Mbps and 100-Mbps operations with full- and half-duplex support. Figure 6.
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EMAC Functional Architecture www.ti.com Table 11 summarizes the individual EMAC and MDIO signals for the S3MII interface. Table 11. EMAC and MDIO Signals for S3MII Interface Signal Name I/O Description TX_CLK O Transmit clock. The transmit clock is a continuous clock that provides the timing reference for transmit operations. The TXD and TX_SYNC signals are tied to this clock. This clock is 125 MHz at 10- and 100-Mbps operations. TX_SYNC O Transmit Synchronization.
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EMAC Functional Architecture www.ti.com Figure 7.
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EMAC Functional Architecture www.ti.com In the case of the S3MII switch, where the switch has only one TX_SYNC for all ports, external logic is needed to synchronize the TX_SYNC signals from multiple ports or TCI6486/C6472 devices. The TXD signal from the multiple ports should also be synchronized using external logic since the clock-phase relation of different TCI6486/C6472 devices can be different. Figure 8 demonstrates the example mutli-PHY configuration for S3MII. Figure 8.
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EMAC Functional Architecture www.ti.com 2.4 Ethernet Protocol Overview Ethernet provides a reliable, connectionless service to a networking application. A brief overview of the ethernet protocol follows. For more information on the carrier sense multiple access with collision detection (CSMA/CD) access method (ethernet's multiple access protocol), see the IEEE 802.3 standard document. 2.4.1 Ethernet Frame Format All the ethernet technologies use the same frame structure.
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EMAC Functional Architecture 2.4.2 www.ti.com Multiple Access Protocol Nodes in an ethernet local area network are interconnected by a broadcast channel. As a result, when an EMAC port transmits a frame, all of the adapters on the local network receive the frame. Carrier sense multiple access with collision detection (CSMA/CD) algorithms are used when the EMAC operates in half-duplex mode.
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EMAC Functional Architecture www.ti.com 2.5 Programming Interface 2.5.1 Packet Buffer Descriptors The buffer descriptor is a central part of the EMAC module. It determines how the application software describes ethernet packets to be sent and empty buffers to be filled with incoming packet data. The basic descriptor format is shown in Figure 10 and described in Table 13. Figure 10.
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EMAC Functional Architecture www.ti.com For example, consider three packets to be transmitted, Packet A is a single fragment (60 bytes), Packet B is fragmented over three buffers (1514 bytes total), and Packet C is a single fragment (1514 bytes). Figure 11 shows the linked list of descriptors to describe these three packets. Figure 11.
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EMAC Functional Architecture www.ti.com To add a descriptor or a linked list of descriptors to an EMAC descriptor queue for the first time, the software application writes the pointer to the descriptor or first descriptor of a list to the corresponding HDP register. Note that the last descriptor in the list must have its next pointer cleared so that the EMAC can detect the end of the list. If only a single descriptor is added, its next descriptor pointer must be initialized to zero.
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EMAC Functional Architecture 2.5.4 www.ti.com Transmit Buffer Descriptor Format A transmit (TX) buffer descriptor (Figure 12) is a contiguous block of four 32-bit data words aligned on a 32-bit boundary that describes a packet or a packet fragment. Example 1 shows the transmit buffer descriptor described by a C structure. Figure 12.
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EMAC Functional Architecture www.ti.com 2.5.4.1 Next Descriptor Pointer The next descriptor pointer indicates the 32-bit word aligned memory address of the next buffer descriptor in the transmit queue. The pointer creates a linked list of buffer descriptors. If the value of this pointer is zero, then the current buffer is the last buffer in the queue. The software application must set this value prior to adding the descriptor to the active transmit list. The pointer is not altered by the EMAC.
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EMAC Functional Architecture 2.5.4.7 www.ti.com End-of-Packet (EOP) Flag When set, this flag indicates that the descriptor points to the last packet buffer for a given packet. For a single fragment packet, both the start-of-packet (SOP) and EOP flags are set. Otherwise, the descriptor pointing to the last packet buffer for the packet sets the EOP flag. This bit is set by the software application and is not altered by the EMAC. 2.5.4.
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EMAC Functional Architecture www.ti.com 2.5.5 Receive Buffer Descriptor Format A receive (RX) buffer descriptor (Figure 13) is a contiguous block of four 32-bit data words aligned on a 32-bit boundary that describes a packet or a packet fragment. Example 2 shows the receive descriptor described by a C structure. Figure 13.
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EMAC Functional Architecture 2.5.5.1 www.ti.com Next Descriptor Pointer The next descriptor pointer indicates the 32-bit word aligned memory address of the next buffer descriptor in the receive queue. The pointer creates a linked list of buffer descriptors. If the value of the pointer is zero, then the current buffer is the last buffer in the queue. The software application must set this value prior to adding the descriptor to the active receive list. This pointer is not altered by the EMAC.
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EMAC Functional Architecture www.ti.com 2.5.5.7 End-of-Packet (EOP) Flag When set, this flag indicates that the descriptor points to the last packet buffer for a given packet. For a single fragment packet, both the start-of-packet (SOP) and EOP flags are set. Otherwise, the descriptor pointing to the last packet buffer for the packet has the EOP flag set. The software application initially clears this flag before adding the descriptor to the receive queue. The EMAC sets this bit on EOP descriptors. 2.5.
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EMAC Functional Architecture 2.5.5.16 www.ti.com Control Flag The EMAC sets this flag in the SOP buffer descriptor if the received packet is an EMAC control frame and was not discarded because the RXCMFEN bit was set in the RXMBPENABLE register. 2.5.5.17 Overrun Flag The EMAC sets this flag in the SOP buffer descriptor if the received packet was aborted due to a receive overrun. 2.5.5.
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EMAC Functional Architecture www.ti.com • • • • – Interrupt combiner Common Interrupt Combiner (CIC) Prescaler Registers CFG peripheral bus interface Figure 14.
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EMAC Functional Architecture 2.7.1 www.ti.com Pacing Block In simple terms, interrupt pacing represents delaying the initial EMAC events to CPU interrupt based on certain criteria. The pacing block is the basic building block for the interrupt pacing operation.
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EMAC Functional Architecture www.ti.com 2.7.2 Timed Delay State Machine (TDSM) The timed-delay state machine fully implements the functionality of the time-delay based interrupt pacing. The TIME_CFG bit field of the TPCFG and RPCFG registers (described in Section 3) is set to 0 on reset and disables this state machine. When the TIME_CFG is set to a non-zero value, an output pulse is generated after the TIME_CFG number of prescalar output periods. The counter starts counting on the first event.
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EMAC Functional Architecture 2.7.3 www.ti.com Divide-by-N State Machine (DSM) The divide-by-N state machine fully implements the functionality of the count-based interrupt pacing. The CNT_CFG bit field of the TPCFG and RPCFG registers (described in Section 3) is set to 0 on reset and immediately generates a pulse (basically means a zero delay), when the TIME_CFG is also set to 0 (i.e., timed-delay SM is disabled). When the TIME_CFG is set to non-zero, it then disables the divide-by-N state machine.
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EMAC Functional Architecture www.ti.com 2.7.4 Transmit Pacer and Interrupt Combiner (TPIC) The transmit pacer and interrupt combiner (TPIC) block performs the following functions: • Optionally implements pacing for transmit events. • Combines the output of the pacer module based on the settings of the bits 8 to 15 in the EW_INTCTL register and generates a single MACTXINT interrupt per the C64x+ megamodule. • Receives a single PS_TICK and forwards it to all the pacing blocks.
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EMAC Functional Architecture 2.7.5 www.ti.com Receive Pacer and Interrupt Combiner (RPIC) The receive pacer and interrupt combiner (RPIC) block performs following functions: • Implements pacing for receive events. • Combines the output of the pacer module based on the settings of bits 16 to 23 in the EW_INTCTL register and generates a single MACRXINT interrupt per the C64x+ megamodule. • Receives a single PS_TICK and forwards it to all the pacing blocks.
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EMAC Functional Architecture www.ti.com 2.7.6 Common Interrupt Combiner (CIC) The common interrupt combiner (CIC) block performs following functions: • Combines the two common interrupts from EMAC (HOST and STAT) with the two MDIO interrupts (MDIO_LINT and MDIO_USER) and generates a single MACINT interrupt per theC64x+ megamodule. • Performs a level-to-pulse conversion of the interrupts because the interrupts from EMAC and MDIO are level sensitive and the C64x+ megamodule expects a pulse interrupt.
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EMAC Functional Architecture www.ti.com Figure 21. MDIO Module Block Diagram Peripheral clock MDIO clock generator USERINT MDIO interface EMIC module LINKINT Configuration bus 2.8.1.1 PHY monitoring MDCLK MDIO PHY polling Control registers and logic MDIO Clock Generator The MDIO clock generator controls the MDIO clock based on a divide-down of the peripheral clock (CPUCLK/6). The MDIO clock is specified to run up to 2.5 MHz, although typical operation would be 1.0 MHz.
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EMAC Functional Architecture www.ti.com 2.8.2 MDIO Module Operational Overview The MDIO module implements the 802.3 serial management interface to simultaneously interrogate and control up to two Ethernet PHYs, using a shared two-wired bus. It separately performs auto-detection and records the current link status of up to 32 PHYs, polling all 32 MDIO addresses.
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EMAC Functional Architecture 2.8.2.2 www.ti.com Writing Data to a PHY Register The MDIO module includes a user access register (USERACCESSn) to directly access a specified PHY device. To write a PHY register, perform the following: 1. Ensure that the GO bit in the USERACCESSn register is cleared. 2. Write to the GO, WRITE, REGADR, PHYADR, and DATA bits in USERACCESSn corresponding to the desired PHY and PHY register. 3. The write operation to the PHY is scheduled and completed by the MDIO module.
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EMAC Functional Architecture www.ti.com The implementation of these macros using the register layer Chip Support Library (CSL) is shown in Example 3 (USERACCESS0 is assumed). Note that this implementation does not check the ACK bit on PHY register reads; in other words, it does not follow the procedure outlined in Section 2.8.2.3. As the ALIVE register initially selects a PHY, it is assumed that the PHY is acknowledging read operations.
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EMAC Functional Architecture 2.9 www.ti.com EMAC Module This section discusses the architecture and basic functions of the EMAC sub-module integrated with the TCI6486/C6472 device. 2.9.1 EMAC Module Components There are two EMAC modules integrated with the TCI6486/C6472 device. EMAC0 interfaces with PHY through one of five interfaces: MII, GMII, S3MII, RMII, or RGMII. EMAC1 interfaces with PHY through one of three interfaces: S3MII, RMII, or RGMII.
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EMAC Functional Architecture www.ti.com • • • • • • 2.9.2 can be sent to only a single channel. The transmit path: – Transmit DMA engine The transmit DMA engine performs the data transfer between the device internal or external memory and the transmit FIFO. It interfaces to the processor through the bus arbiter in the CPPI buffer manager. This DMA engine is totally independent of the TCI6486/C6472 DSP EDMA.
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EMAC Functional Architecture www.ti.com An interrupt is issued to the CPU whenever a transmit or receive operation has completed. However, it is not necessary for the CPU to service the interrupt while there are additional resources available. In other words, the EMAC continues to receive Ethernet packets until its receive descriptor list has been exhausted. On transmit operations, the transmit descriptors need only be serviced to recover their associated memory buffer.
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EMAC Functional Architecture www.ti.com Receive buffer flow control is triggered when the number of free buffers in any enabled receive channel (RXnFREEBUFFER) is less than or equal to the channel flow control threshold register (RXnFLOWTHRESH) value. Receive flow control is independent of receive QOS, except that both use the free buffer values. When enabled and triggered, receive FIFO flow control prevents further frame reception based on the number of cells currently in the receive FIFO.
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EMAC Functional Architecture • • www.ti.com Zero padding to 64-byte data length (EMAC transmits only 64-byte pause frames). The 32-bit frame-check sequence (CRC word). All quantities are hexadecimal and are transmitted most-significant-byte first. The least-significant-bit (LSB) is transferred first in each byte. If the RXBUFFERFLOWEN bit in the MACCONTROL register is cleared while the pause time is nonzero, then the pause time is cleared and a zero count pause frame is sent. 2.10.
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EMAC Functional Architecture www.ti.com 2.10.2.5 Back Off The EMAC implements the 802.3 binary exponential back-off algorithm. 2.10.2.6 Transmit Flow Control When enabled, incoming pause frames are acted upon to prevent the EMAC from transmitting any further frames. Incoming pause frames are only acted upon when the FULLDUPLEX and TXFLOWEN bits in the MACCONTROL register are set. Pause frames are not acted upon in half-duplex mode.
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EMAC Functional Architecture 2.10.2.7 www.ti.com Speed, Duplex, and Pause Frame Support The MAC can operate in half-duplex or full-duplex mode at 10 Mbps or 100 Mbps, and can operate in full duplex only in 1000 Mbps. Pause frame support is included in 10/100/1000 Mbps modes as configured by the host. 2.11 Packet Receive Operation 2.11.1 Receive DMA Host Configuration To • • • • • • • • • • 2.11.
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EMAC Functional Architecture www.ti.com A MAC address location in RAM is 53 bits wide and consists of: • 48 bits of the MAC address • 3 bits for the channel to which a valid address match will be transferred. The channel is a don't care if the MATCHFILT bit is cleared. • A valid bit • A match or filter bit First, write the index into the address RAM in the MACINDEX register to start writing a MAC address.
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EMAC Functional Architecture 2.11.6 www.ti.com Receive Channel Teardown The host commands a receive channel teardown by writing the channel number to the RXTEARDOWN register. When a teardown command is issued to an enabled receive channel, the following occurs: • Any current frame in reception completes normally. • The TDOWNCMPLT flag is set in the next buffer descriptor in the chain, if there is one. • The channel head descriptor pointer is cleared.
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EMAC Functional Architecture www.ti.com 2.11.8 Promiscuous Receive Mode When the promiscuous receive mode is enabled by setting the RXCAFEN bit in the RXMBPENABLE register, non-address matching frames that would normally be filtered are transferred to the promiscuous channel. Address matching frames that would normally be filtered due to errors are transferred to the address match channel when the RXCAFEN and RXCEFEN bits are set.
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EMAC Functional Architecture www.ti.com Table 14. Receive Frame Treatment Summary (continued) Address Match 2.11.9 RXMBPENABLE Bits RXCAFEN RXCEFEN RXCMFEN RXCSFEN Frame Treatment 1 X 1 1 0 Proper/oversize/jabber/code/align/CRC data and control frames transferred to address match channel. No undersized/fragment frames are transferred. 1 X 1 1 1 All address matching frames with and without errors transferred to the address match channel.
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EMAC Functional Architecture www.ti.com • • • • • • 2.12.2 Initialize the TXnHDP registers to zero. Enable the desired transmit interrupts using the TXINTMASKSET and TXINTMASKCLEAR registers. Set the appropriate configuration bits in the MACCONTROL register. Set up the transmit channel(s) buffer descriptors in host memory. Enable the transmit DMA controller by setting the TXEN bit in the TXCONTROL register.
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EMAC Functional Architecture www.ti.com For example, for 1000-Mbps operation, these restrictions translate into the following rules: • For the short-term average, each 64-byte memory read/write request from the EMAC must be serviced in no more than 0.512 ms. • Any single latency event in request servicing can be no longer than (0.512 * TXCELLTHRESH) ms. Bits [0-2] of the PRI_ALLOC register set the transfer node priority for EMAC0 in the device.
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EMAC Functional Architecture www.ti.com 2.16 Initialization 2.16.1 Enabling the EMAC/MDIO Peripheral When the device is powered on, the EMAC peripheral is disabled. Prior to EMAC-specific initialization, the EMAC must be enabled; otherwise its registers cannot be written, and the reads will all return a value of zero. The interface to be used (MII, RMII, GMII, or RGMII) is automatically selected at power-on reset, based on the state of the MACSEL configuration pins.
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EMAC Functional Architecture www.ti.com If the MDIO module must operate on an interrupt basis, the interrupts can be enabled at this time using the USERINTMASKSET register for register access and the USERPHYSELn register if a target PHY is already known. Once the MDIO state machine has been initialized and enabled, it starts polling all 32 PHY addresses on the MDIO bus, looking for active PHYs.
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EMAC Functional Architecture www.ti.com Configuration register (EMACCFG), found at device level. 20. Enable the device interrupt in EW_INTCTL. 2.17 Interrupt Support 2.17.1 EMAC Module Interrupt Events and Requests The EMAC/MDIO generates 18 interrupt events, as follows: • TXPENDn: Transmit packet completion interrupt for transmit channels 7 through 0 • RXPENDn: Receive packet completion interrupt for receive channels 7 through 0 • STATPEND: Statistics interrupt • HOSTPEND: Host error interrupt 2.17.1.
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EMAC Functional Architecture www.ti.com Upon interrupt reception, the CPU processes one or more packets from the buffer chain and then acknowledges one or more interrupt(s) by writing the address of the last buffer descriptor processed to the queue's associated RX completion pointer in the receive DMA state RAM.
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EMAC Functional Architecture www.ti.com 2.17.2.1 Link Change Interrupt The MDIO module asserts a link change interrupt (LINKINT) if there is a change in the link state of the PHY corresponding to the address in the PHYADRMON bits in the USERPHYSELn register, and if the LINKINTENB bit is also set in USERPHYSELn. This interrupt event is also captured in the LINKINTRAW bits of the LINKINTRAW register. The LINKINTRAW bits 0 and 1 correspond to USERPHYSEL0 and USERPHYSEL1, respectively.
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EMAC Functional Architecture www.ti.com When the emulation suspend state is entered, the EMAC will stop processing receive and transmit frames at the next frame boundary. Any frame currently in reception or transmission will be completed normally without suspension. For transmission, any complete or partial frame in the transmit cell FIFO will be transmitted. For receive, frames that are detected by the EMAC after the suspend state is entered are ignored. No statistics will be kept for ignored frames.
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EMIC Module Registers www.ti.com 3 EMIC Module Registers 3.1 EW_INTCTL Registers There are six EW_INTCTL registers (one per C64x+ megamodule). These registers, shown in Figure 23, reside in the configuration space of the respective Ethernet wrappers. This register controls generation of MACTXINT, MACRXINT, and MACINT interrupts for each core.
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EMIC Module Registers www.ti.com Figure 24. RPCFG Register 31 28 27 16 Reserved TIME_CFG 0000 R/W-0000 0000 15 3 2 1 0 CNT_CFG 8 7 Reserved 4 TU CU TR CR R/W-0000 0000 0000 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 17.
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EMIC Module Registers www.ti.com 3.2.2 RPSTAT Registers There are eight RPSTAT registers (RPSTAT0 thru RPSTAT7), one per receive event. This register configuration is common to all C64x+ megamodules. The RPSTAT register details are shown in Figure 25 and described in Table 18. Figure 25.
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EMIC Module Registers 3.3 www.ti.com TPIC Registers 3.3.1 TPCFG Registers There are eight TPCFG registers (TPCFG0 through TPCFG7), one per transmit event. This register configuration is common to all C64x+ megamodules. The TPCFG register details are shown in Figure 26 and described in Table 19. Figure 26.
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EMIC Module Registers www.ti.com 3.3.2 TPSTAT Registers There are eight TPSTAT registers (TPSTAT0 through TPSTAT7), one per transmit event. This register configuration is common to all C64x+mega modules. The TPSTAT register details are shown in Figure 27 and described in Table 20. Figure 27.
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MDIO Registers www.ti.com 4 MDIO Registers 4.1 Introduction Table 21 lists the memory-mapped registers for the Management Data Input/Output (MDIO). For the memory address of these registers, see the TMS320TCI6486 Communications Infrastructure Digital Signal Processor data manual (SPRS300) or the TMS320C6472 Fixed-Point Digital Signal Processor data manual (SPRS612). Table 21.
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MDIO Registers www.ti.com 4.2 MDIO Version Register (VERSION) The MDIO version register (VERSION) is shown in Figure 29 and described in Table 22. Figure 29. MDIO Version Register (VERSION) 31 16 MODID R-7 15 8 7 0 REVMAJ REVMIN R-1 R-3 LEGEND: R = Read only; R/W = Read/Write; -n = value after reset Table 22.
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MDIO Registers 4.3 www.ti.com MDIO Control Register (CONTROL) The MDIO control register (CONTROL) is shown in Figure 30 and described in Table 23. Figure 30. MDIO Control Register (CONTROL) 31 30 29 28 24 23 21 20 19 18 Reserved R-0 IDLE ENABLE Reserved HIGHEST_USER_CHANNEL Reserved PREAMBLE FAULT FAULT ENB R-1 R/W-0 R-0 R-1 R-0 R/W-0 R/WC-0 R/W-0 17 16 15 0 CLKDIV R/W-255 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 23.
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MDIO Registers www.ti.com 4.4 PHY Acknowledge Status Register (ALIVE) The PHY acknowledge status register (ALIVE) is shown in Figure 31 and described in Table 24. Figure 31. PHY Acknowledge Status Register (ALIVE) 31 16 ALIVE R/WC-0 15 0 ALIVE R/WC-0 LEGEND: R/W = Read/Write; R/WC = Read/Write 1 to clear; -n = value after reset Table 24. PHY Acknowledge Status Register (ALIVE) Field Descriptions Bit Field 31-0 ALIVE Value Description MDIO Alive bits.
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MDIO Registers 4.5 www.ti.com PHY Link Status Register (LINK) The PHY link status register (LINK) is shown in Figure 32 and described in Table 25. Figure 32. PHY Link Status Register (LINK) 31 16 LINK R-0 15 0 LINK R-0 LEGEND: R = Read only; -n = value after reset Table 25. PHY Link Status Register (LINK) Field Descriptions 80 Bit Field 31-0 LINK Value Description MDIO Link state bits. This register is updated after a read of the Generic Status Register of a PHY.
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MDIO Registers www.ti.com 4.6 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) The MDIO link status change interrupt (unmasked) register (LINKINTRAW) is shown in Figure 33 and described in Table 26. Figure 33. MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) 31 16 Reserved R-0 15 2 1 0 Reserved LINKINTRAW R-0 R/WC-0 LEGEND: R = Read only; R/WC = Read/Write 1 to clear; -n = value after reset Table 26.
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MDIO Registers 4.7 www.ti.com MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) The MDIO link status change interrupt (masked) register (LINKINTMASKED) is shown in Figure 34 and described in Table 27. Figure 34. MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) 31 16 Reserved R-0 15 2 1 0 Reserved LINKINT MASKED R-0 R/WC-0 LEGEND: R = Read only; R/WC = Read/Write 1 to clear; -n = value after reset Table 27.
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MDIO Registers www.ti.com 4.8 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) The MDIO user command complete interrupt (unmasked) register (USERINTRAW) is shown in Figure 35 and described in Table 28. Figure 35. MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) 31 16 Reserved R-0 15 2 1 0 Reserved USERINTRAW R-0 R/WC-0 LEGEND: R = Read only; R/WC = Read/Write 1 to clear; -n = value after reset Table 28.
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MDIO Registers 4.9 www.ti.com MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) The MDIO user command complete interrupt (masked) register (USERINTMASKED) is shown in Figure 36 and described in Table 29. Figure 36. MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) 31 16 Reserved R-0 15 2 1 0 Reserved USERINT MASKED R-0 R/WC-0 LEGEND: R = Read only; R/WC = Read/Write 1 to clear; -n = value after reset Table 29.
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MDIO Registers www.ti.com 4.10 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) The MDIO user command complete interrupt mask set register (USERINTMASKSET) is shown in Figure 37 and described in Table 30. Figure 37. MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) 31 16 Reserved R-0 15 2 1 0 Reserved USERINT MASKSET R-0 R/WC-0 LEGEND: R = Read only; R/WC = Read/Write 1 to clear; -n = value after reset Table 30.
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MDIO Registers www.ti.com 4.11 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) The MDIO user command complete interrupt mask clear register (USERINTMASKCLEAR) is shown in Figure 38 and described in Table 31. Figure 38. MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) 31 16 Reserved R-0 15 2 1 0 Reserved USERINT MASKCLEAR R-0 R/WC-0 LEGEND: R = Read only; R/WC = Read/Write 1 to clear; -n = value after reset Table 31.
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MDIO Registers www.ti.com 4.12 MDIO User Access Register 0 (USERACCESS0) The MDIO user access register 0 (USERACCESS0) is shown in Figure 39 and described in Table 32. Figure 39. MDIO User Access Register 0 (USERACCESS0) 31 30 29 28 GO WRITE ACK Reserved 26 25 REGADR 21 20 PHYADR 16 R/WS-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 15 0 DATA R/W-0 LEGEND: R = Read only; R/W = Read/Write; R/WS = Read/Write 1 to set; -n = value after reset Table 32.
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MDIO Registers www.ti.com 4.13 MDIO User PHY Select Register 0 (USERPHYSEL0) The MDIO user PHY select register 0 (USERPHYSEL0) is shown in Figure 40 and described in Table 33. Figure 40. MDIO User PHY Select Register 0 (USERPHYSEL0) 31 16 Reserved R-0 15 7 6 5 Reserved 8 LINKSEL LINKINTENB Reserved 4 PHYADRMON 0 R-0 R/W-0 R/W-0 R-0 R/W-0 LEGEND: R = Read only; R/W = Read/Write; -n = value after reset Table 33.
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MDIO Registers www.ti.com 4.14 MDIO User Access Register 1 (USERACCESS1) The MDIO user access register 1 (USERACCESS1) is shown in Figure 41 and described in Table 34. Figure 41. MDIO User Access Register 1 (USERACCESS1) 31 30 29 28 GO WRITE ACK Reserved 26 25 REGADR 21 20 PHYADR 16 R/WS-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 15 0 DATA R/W-0 LEGEND: R = Read only; R/W = Read/Write; R/WS = Read/Write 1 to set; -n = value after reset Table 34.
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MDIO Registers www.ti.com 4.15 MDIO User PHY Select Register 1 (USERPHYSEL1) The MDIO user PHY select register 1 (USERPHYSEL1) is shown in Figure 42 and described in Table 35. Figure 42. MDIO User PHY Select Register 1 (USERPHYSEL1) 31 16 Reserved R-0 15 7 6 5 Reserved 8 LINKSEL LINKINTENB Reserved 4 PHYADRMON 0 R-0 R/W-0 R/W-0 R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 35.
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EMAC Port Registers www.ti.com 5 EMAC Port Registers Table 36 lists the memory-mapped registers for the Ethernet Media Access Controller (EMAC). For the memory address of these registers, see the TMS320TCI6486 Communications Infrastructure Digital Signal Processor data manual (SPRS300) or the TMS320C6472 Fixed-Point Digital Signal Processor data manual (SPRS612). Table 36.
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EMAC Port Registers www.ti.com Table 36. Ethernet Media Access Controller (EMAC) Registers (continued) 92 Offset Acronym Register Description 15Ch RX7FREEBUFFER Receive Channel 7 Free Buffer Count Register Section 5.28 See 160h MACCONTROL MAC Control Register Section 5.29 164h MACSTATUS MAC Status Register Section 5.30 168h EMCONTROL Emulation Control Register Section 5.31 16Ch FIFOCONTROL FIFO Control Register Section 5.32 170h MACCONFIG MAC Configuration Register Section 5.
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EMAC Port Registers www.ti.com Table 36. Ethernet Media Access Controller (EMAC) Registers (continued) Offset Acronym Register Description 65Ch TX7CP Transmit Channel 7 Completion Pointer (Interrupt Acknowledge) Register Section 5.48 See 660h RX0CP Receive Channel 0 Completion Pointer (Interrupt Acknowledge) Register Section 5.49 664h RX1CP Receive Channel 1 Completion Pointer (Interrupt Acknowledge) Register Section 5.
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EMAC Port Registers www.ti.com Table 36. Ethernet Media Access Controller (EMAC) Registers (continued) 94 Offset Acronym Register Description 27Ch FRAME1024TUP Transmit and Receive 1024 to RXMAXLEN Octet Frames Register Section 5.50.32 280h NETOCTETS Network Octet Frames Register Section 5.50.33 284h RXSOFOVERRUNS Receive FIFO or DMA Start-of-Frame Overruns Register Section 5.50.34 288h RXMOFOVERRUNS Receive FIFO or DMA Middle-of-Frame Overruns Register Section 5.50.
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EMAC Port Registers www.ti.com 5.1 Transmit Identification and Version Register (TXIDVER) The transmit identification and version register (TXIDVER) is shown in Figure 43 and described in Table 37. Figure 43. Transmit Identification and Version Register (TXIDVER) 31 16 TXIDENT 0x000C 15 11 10 8 7 0 RTLVER TXMAJORVER TXMINORVER 0x01 0x02 0x08 LEGEND: R = Read only; -n = value after reset Table 37.
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EMAC Port Registers 5.2 www.ti.com Transmit Control Register (TXCONTROL) The transmit control register (TXCONTROL) is shown in Figure 44 and described in Table 38. Figure 44. Transmit Control Register (TXCONTROL) 31 16 Reserved R-0 15 1 0 Reserved TXEN R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 38.
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EMAC Port Registers www.ti.com 5.3 Transmit Teardown Register (TXTEARDOWN) The transmit teardown register (TXTEARDOWN) is shown in Figure 45 and described in Table 39. Figure 45. Transmit Teardown Register (TXTEARDOWN) 31 30 16 TXTD NRDY Reserved R-0 15 3 2 0 Reserved TXTDNCH R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 39. Transmit Teardown Register (TXTEARDOWN) Field Descriptions Bit Field 31 TXTDNRDY Value 0 Description Transmit teardown ready.
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EMAC Port Registers 5.4 www.ti.com Receive Identification and Version Register (RXIDVER) The receive identification and version register (RXIDVER) is shown in Figure 46 and described in Table 40. Figure 46. Receive Identification and Version Register (RXIDVER) 31 16 RXIDENT 0x000C 15 11 10 8 7 0 RTLVER RXMAJORVER RXMINORVER 0x01 0x02 0x08 LEGEND: R = Read only; -n = value after reset Table 40.
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EMAC Port Registers www.ti.com 5.5 Receive Control Register (RXCONTROL) The receive control register (RXCONTROL) is shown in Figure 47 and described in Table 41. Figure 47. Receive Control Register (RXCONTROL) 31 16 Reserved R-0 15 1 0 Reserved RXEN R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 41.
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EMAC Port Registers 5.6 www.ti.com Receive Teardown Register (RXTEARDOWN) The receive teardown register (RXTEARDOWN) is shown in Figure 48 and described in Table 42. Figure 48. Receive Teardown Register (RXTEARDOWN) 31 16 RXTD NRDY Reserved R-0 15 3 2 0 Reserved RXTDNCH R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 42. Receive Teardown Register (RXTEARDOWN) Field Descriptions Bit Field 31 RXTDNRDY 0 Receive teardown ready.
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EMAC Port Registers www.ti.com 5.7 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) The transmit interrupt status (unmasked) register (TXINTSTATRAW) is shown in Figure 49 and described in Table 43. Figure 49.
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EMAC Port Registers 5.8 www.ti.com Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) The transmit interrupt status (masked) register (TXINTSTATMASKED) is shown in Figure 50 and described in Table 44. Figure 50.
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EMAC Port Registers www.ti.com 5.9 Transmit Interrupt Mask Set Register (TXINTMASKSET) The transmit interrupt mask set register (TXINTMASKSET) is shown in Figure 51 and described in Table 45. Figure 51.
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EMAC Port Registers www.ti.com 5.10 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) The transmit interrupt mask clear register (TXINTMASKCLEAR) is shown in Figure 52 and described in Table 46. Figure 52.
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EMAC Port Registers www.ti.com 5.11 MAC Input Vector Register (MACINVECTOR) The MAC input vector register (MACINVECTOR) is shown in Figure 53 and described in Table 47. Figure 53. MAC Input Vector Register (MACINVECTOR) 31 30 USER INT LINK INT R-0 R-0 29 18 15 17 16 Reserved HOST PEND STAT PEND R-0 R-0 R-0 8 7 0 RXPEND TXPEND R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 47.
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EMAC Port Registers www.ti.com 5.12 MAC End-of-Interrupt Vector Register (MACEOIVECTOR) The MAC end-of-interrupt vector register (MACEOIVECTOR) is shown in Figure 54 and described in Table 48. Figure 54. MAC End-of-Interrupt Vector Register (MACEOIVECTOR) 31 5 4 0 Reserved MAC_EOI_VECTOR R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 48.
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EMAC Port Registers www.ti.com 5.13 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) The receive interrupt status (unmasked) register (RXINTSTATRAW) is shown in Figure 55 and described in Table 49. Figure 55.
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EMAC Port Registers www.ti.com 5.14 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) The receive interrupt status (masked) register (RXINTSTATMASKED) is shown in Figure 56 and described in Table 50. Figure 56.
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EMAC Port Registers www.ti.com 5.15 Receive Interrupt Mask Set Register (RXINTMASKSET) The receive interrupt mask set register (RXINTMASKSET) is shown in Figure 57 and described in Table 51. Figure 57.
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EMAC Port Registers www.ti.com 5.16 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) The receive interrupt mask clear register (RXINTMASKCLEAR) is shown in Figure 58 and described in Table 52. Figure 58.
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EMAC Port Registers www.ti.com 5.17 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) The MAC interrupt status (unmasked) register (MACINTSTATRAW) is shown in Figure 59 and described in Table 53. Figure 59. MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) 31 16 Reserved R-0 15 2 1 0 Reserved HOST PEND STAT PEND R-0 R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 53.
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EMAC Port Registers www.ti.com 5.18 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) The MAC interrupt status (masked) register (MACINTSTATMASKED) is shown in Figure 60 and described in Table 54. Figure 60. MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) 31 16 Reserved R-0 15 2 1 0 Reserved HOST PEND STAT PEND R-0 R-0 R-0 LEGEND: R/W = R = Read only; -n = value after reset Table 54.
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EMAC Port Registers www.ti.com 5.19 MAC Interrupt Mask Set Register (MACINTMASKSET) The MAC interrupt mask set register (MACINTMASKSET) is shown in Figure 61 and described in Table 55. Figure 61. MAC Interrupt Mask Set Register (MACINTMASKSET) 31 16 Reserved R-0 15 2 1 0 Reserved HOST MASK STAT MASK R-0 R/WS-0 R/WS-0 LEGEND: R = Read only; R/W = Read/Write; R/WS = Read/Write 1 to set; -n = value after reset Table 55.
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EMAC Port Registers www.ti.com 5.20 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) The MAC interrupt mask clear register (MACINTMASKCLEAR) is shown in Figure 62 and described in Table 56. Figure 62. MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) 31 16 Reserved R-0 15 2 1 0 Reserved HOST MASK STAT MASK R-0 R/WC-0 R/WC-0 LEGEND: R = Read only; R/W = Read/Write; R/WC = Read/Write 1 to clear; -n = value after reset Table 56.
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EMAC Port Registers www.ti.com 5.21 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) The receive multicast/broadcast/promiscuous channel enable register (RXMBPENABLE) is shown in Figure 63 and described in Table 57. Figure 63.
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EMAC Port Registers www.ti.com Table 57. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field Descriptions (continued) Bit Field 22 RXCEFEN 21 Reserved 18-16 RXPROMCH 13 Reserved Reserved 10-8 RXBROADCH 7-6 5 4-3 116 0 Frames containing errors are filtered 1 Frames containing errors are transferred to memory Receive copy all frames enable bit.
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EMAC Port Registers www.ti.com Table 57.
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EMAC Port Registers www.ti.com 5.22 Receive Unicast Enable Set Register (RXUNICASTSET) The receive unicast enable set register (RXUNICASTSET) is shown in Figure 64 and described in Table 58. Figure 64.
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EMAC Port Registers www.ti.com 5.23 Receive Unicast Clear Register (RXUNICASTCLEAR) The receive unicast clear register (RXUNICASTCLEAR) is shown in Figure 65 and described in Table 59. Figure 65.
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EMAC Port Registers www.ti.com 5.24 Receive Maximum Length Register (RXMAXLEN) The receive maximum length register (RXMAXLEN) is shown in Figure 66 and described in Table 60. Figure 66. Receive Maximum Length Register (RXMAXLEN) 31 16 Reserved R-0 15 0 RXMAXLEN R/W-1518 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 60.
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EMAC Port Registers www.ti.com 5.25 Receive Buffer Offset Register (RXBUFFEROFFSET) The receive buffer offset register (RXBUFFEROFFSET) is shown in Figure 67 and described in Table 61. Figure 67. Receive Buffer Offset Register (RXBUFFEROFFSET) 31 16 Reserved R-0 15 0 RXBUFFEROFFSET R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 61.
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EMAC Port Registers www.ti.com 5.26 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) The receive filter low priority frame threshold register (RXFILTERLOWTHRESH) is shown in Figure 68 and described in Table 62. Figure 68. Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) 31 16 Reserved R-0 15 8 7 0 Reserved RXFILTERTHRESH R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 62.
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EMAC Port Registers www.ti.com 5.27 Receive Channel 0-7 Flow Control Threshold Register (RXnFLOWTHRESH) The receive channel 0-7 flow control threshold register (RXnFLOWTHRESH) is shown in Figure 69 and described in Table 63. Figure 69. Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH) 31 16 Reserved R-0 15 8 7 0 Reserved RXnFLOWTHRESH R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 63.
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EMAC Port Registers www.ti.com 5.28 Receive Channel 0-7 Free Buffer Count Register (RXnFREEBUFFER) The receive channel 0-7 free buffer count register (RXnFREEBUFFER) is shown in Figure 70 and described in Table 64. Figure 70. Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) 31 16 Reserved R-0 15 0 RXnFREEBUF WI-0 tLEGEND: R = Read only; R/W = Read/Write; WI = Write to increment; -n = value after reset Table 64.
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EMAC Port Registers www.ti.com 5.29 MAC Control Register (MACCONTROL) The MAC control register (MACCONTROL) is shown in Figure 71 and described in Table 65. Figure 71.
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EMAC Port Registers www.ti.com Table 65. MAC Control Register (MACCONTROL) Field Descriptions (continued) Bit Field 12 RXFIFOFLOWEN 11 Reserved 9 TXPTYPE 8 Reserved 7 GIG 5 4 3 126 Receive flow control disabled. For full-duplex mode, no outgoing pause frames are sent. 1 Receive flow control enabled. For full-duplex mode, outgoing pause frames are sent when receive FIFO flow control is triggered.
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EMAC Port Registers www.ti.com 5.30 MAC Status Register (MACSTATUS) The MAC status register (MACSTATUS) is shown in Figure 72 and described in Table 66. Figure 72.
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EMAC Port Registers www.ti.com Table 66. MAC Status Register (MACSTATUS) Field Descriptions (continued) Bit 15-12 11 10-8 Field Value RXERRCODE Reserved RXERRCH Description Receive host error code. These bits indicate that EMAC detected receive DMA related host errors. The host should read this field after a host error interrupt (HOSTPEND) to determine the error. Host error interrupts require a hardware reset in order to recover. 0 No error 2h Ownership bit not set in SOP buffer.
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EMAC Port Registers www.ti.com 5.31 Emulation Control Register (EMCONTROL) The emulation control register (EMCONTROL) is shown in Figure 73 and described in Table 67. Figure 73. Emulation Control Register (EMCONTROL) 31 16 Reserved R-0 15 1 0 Reserved 2 SOFT FREE R-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 67.
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EMAC Port Registers www.ti.com 5.32 FIFO Control Register (FIFOCONTROL) The FIFO control register (FIFOCONTROL) is shown in Figure 74 and described in Table 68. Figure 74. FIFO Control Register (FIFOCONTROL) 31 23 22 16 Reserved RXFIFOFLOWTHRESH R-0 R/W-2 15 5 4 0 Reserved TXCELLTHRESH R-0 R/W-24 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 68.
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EMAC Port Registers www.ti.com 5.33 MAC Configuration Register (MACCONFIG) The MAC configuration register (MACCONFIG) is shown in Figure 75 and described in Table 69. Figure 75. MAC Configuration Register (MACCONFIG) 31 24 23 16 TXCELLDEPTH RXCELLDEPTH R-24 R-68 15 8 7 0 ADDRESSTYPE MACCFIG R-2 R-3 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 69.
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EMAC Port Registers www.ti.com 5.34 Soft Reset Register (SOFTRESET) The soft reset register (SOFTRESET) is shown in Figure 76 and described in Table 70. Figure 76. Soft Reset Register (SOFTRESET) 31 16 Reserved R-0 15 1 0 Reserved SOFTRESET R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 70. Soft Reset Register (SOFTRESET) Field Descriptions Bit 31-1 0 132 Field Reserved Value 0 SOFTRESET Description Reserved Software reset.
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EMAC Port Registers www.ti.com 5.35 MAC Source Address Low Bytes Register (MACSRCADDRLO) The MAC source address low bytes register (MACSRCADDRLO) is shown in Figure 77 and described in Table 71. Figure 77. MAC Source Address Low Bytes Register (MACSRCADDRLO) 31 16 Reserved R-0 15 8 7 0 MACSRCADDR0 MACSRCADDR1 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 71.
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EMAC Port Registers www.ti.com 5.36 MAC Source Address High Bytes Register (MACSRCADDRHI) The MAC source address high bytes register (MACSRCADDRHI) is shown in Figure 78 and described in Table 72. Figure 78. MAC Source Address High Bytes Register (MACSRCADDRHI) 31 24 23 16 MACSRCADDR2 MACSRCADDR3 R/W-0 R/W-0 15 8 7 0 MACSRCADDR4 MACSRCADDR5 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 72.
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EMAC Port Registers www.ti.com 5.37 MAC Hash Address Register 1 (MACHASH1) The MAC hash registers allow group addressed frames to be accepted on the basis of a hash function of the address.
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EMAC Port Registers www.ti.com 5.38 MAC Hash Address Register 2 (MACHASH2) The MAC hash address register 2 (MACHASH2) is shown in Figure 80 and described in Table 74. Figure 80. MAC Hash Address Register 2 (MACHASH2) 31 16 MACHASH2 R/W-0 15 0 MACHASH2 R/W-0 LEGEND: R/W = Read/Write; -n = value after reset Table 74.
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EMAC Port Registers www.ti.com 5.39 Back Off Test Register (BOFFTEST) The back off test register (BOFFTEST) is shown in Figure 81 and described in Table 75. Figure 81. Back Off Test Register (BOFFTEST) 31 26 25 16 Reserved RNDNUM R-0 R-0 15 12 11 10 9 0 COLLCOUNT Reserved TXBACKOFF R-0 R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 75.
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EMAC Port Registers www.ti.com 5.40 Transmit Pacing Algorithm Test Register (TPACETEST) The transmit pacing algorithm test register (TPACETEST) is shown in Figure 82 and described in Table 76. Figure 82. Transmit Pacing Algorithm Test Register (TPACETEST) 31 16 Reserved R-0 15 5 4 0 Reserved PACEVAL R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 76.
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EMAC Port Registers www.ti.com 5.41 Receive Pause Timer Register (RXPAUSE) The receive pause timer register (RXPAUSE) is shown in Figure 83 and described in Table 77. Figure 83. Receive Pause Timer Register (RXPAUSE) 31 16 Reserved R-0 15 0 PAUSETIMER R-0 LEGEND: R = Read only; -n = value after reset Table 77. Receive Pause Timer Register (RXPAUSE) Field Descriptions Bit Field 31-16 Reserved 15-0 PAUSETIMER Value 0 Description Reserved Receive pause timer value.
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EMAC Port Registers www.ti.com 5.42 Transmit Pause Timer Register (TXPAUSE) The transmit pause timer register (TXPAUSE) is shown in Figure 84 and described in Table 78. Figure 84. Transmit Pause Timer Register (TXPAUSE) 31 16 Reserved R-0 15 0 PAUSETIMER R-0 LEGEND: R = Read only; -n = value after reset Table 78.
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EMAC Port Registers www.ti.com 5.43 MAC Address Low Bytes Register (MACADDRLO) The MAC address low bytes register (MACADDRLO) is shown in Figure 85 and described in Table 79. Figure 85. MAC Address Low Bytes Register (MACADDRLO) 31 21 20 19 Reserved VALID MATCH FILT CHANNEL R-0 R/W-x R/W-x R/W-x 15 8 18 16 7 0 MACADDR0 MACADDR1 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 79.
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EMAC Port Registers www.ti.com 5.44 MAC Address High Bytes Register (MACADDRHI) The MAC address high bytes register (MACADDRHI) is shown in Figure 86 and described in Table 80. Figure 86. MAC Address High Bytes Register (MACADDRHI) 31 24 23 16 MACADDR2 MACADDR3 R/W-0 R/W-0 15 8 7 0 MACADDR4 MACADDR5 R/W-0 R/W-0 LEGEND: R/W = Read/Write; -n = value after reset Table 80.
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EMAC Port Registers www.ti.com 5.45 MAC Index Register (MACINDEX) The MAC index register (MACINDEX) is shown in Figure 87 and described in Table 81. Figure 87. MAC Index Register (MACINDEX) 31 16 Reserved R-0 15 5 4 0 Reserved MACINDEX R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 81. MAC Index Register (MACINDEX) Field Descriptions Bit Field 31-5 Reserved 4-0 MACINDEX Value 0 Description Reserved MAC address index.
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EMAC Port Registers www.ti.com 5.46 Transmit Channel 0-7 DMA Head Descriptor Pointer Register (TXnHDP) The transmit channel 0-7 DMA head descriptor pointer register (TXnHDP) is shown in Figure 88 and described in Table 82. Figure 88. Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP) 31 16 TXnHDP R/W-x 15 0 TXnHDP R/W-x LEGEND: R/W = Read/Write; -n = value after reset Table 82.
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EMAC Port Registers www.ti.com 5.47 Receive Channel 0-7 DMA Head Descriptor Pointer Register (RXnHDP) The receive channel 0-7 DMA head descriptor pointer register (RXnHDP) is shown in Figure 89 and described in Table 83. Figure 89. Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP) 31 16 RXnHDP R/W-x 15 0 RXnHDP R/W-x LEGEND: R/W = Read/Write; -n = value after reset Table 83.
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EMAC Port Registers www.ti.com 5.48 Transmit Channel 0-7 Completion Pointer Register (TXnCP) The transmit channel 0-7 completion pointer register (TXnCP) is shown in Figure 90 and described in Table 84. Figure 90. Transmit Channel n Completion Pointer Register (TXnCP) 31 16 TXnCP R/W-x 15 0 TXnCP R/W-x LEGEND: R/W = Read/Write; -n = value after reset Table 84.
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EMAC Port Registers www.ti.com 5.49 Receive Channel 0-7 Completion Pointer Register (RXnCP) The receive channel 0-7 completion pointer register (RXnCP) is shown in Figure 91 and described in Table 85. Figure 91. Receive Channel n Completion Pointer Register (RXnCP) 31 16 RXnCP R/W-x 15 0 RXnCP R/W-x LEGEND: R/W = Read/Write; -n = value after reset Table 85.
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EMAC Port Registers www.ti.com 5.50 Network Statistics Registers The EMAC has a set of statistics that record events associated with frame traffic. The statistics values are cleared to zero 38 clocks after the rising edge of reset. When the GMIIEN bit in the MACCONTROL register is set, all statistics registers are write-to-decrement. The value written is subtracted from the register value with the result stored in the register.
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EMAC Port Registers www.ti.com 5.50.3 Multicast Receive Frames Register (RXMCASTFRAMES) The total number of good multicast frames received on the EMAC. A good multicast frame is defined as having all of the following: • Any data or MAC control frame that was destined for any multicast address other than FF-FF-FF-FF-FF-FFh • Was of length 64 to RXMAXLEN bytes inclusive • Had no CRC error, alignment error, or code error See Section 2.5.5 for alignment/code/CRC error definitions.
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EMAC Port Registers 5.50.7 www.ti.com Receive Oversized Frames Register (RXOVERSIZED) The total number of oversized frames received on the EMAC. An oversized frame is defined as having all of the following: • Was any data or MAC control frame that matched a unicast, broadcast, or multicast address, or matched due to promiscuous mode • Was greater than RXMAXLEN in bytes • Had no CRC error, alignment error, or code error See Section 2.5.5 for definitions of alignment, code/CRC errors.
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EMAC Port Registers www.ti.com 5.50.11 Filtered Receive Frames Register (RXFILTERED) The total number of frames received on the EMAC that the EMAC address matching process indicated should be discarded.
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EMAC Port Registers www.ti.com 5.50.15 Broadcast Transmit Frames Register (TXBCASTFRAMES) The total number of good broadcast frames transmitted on the EMAC. A good broadcast frame is defined as having all of the following: • Any data or MAC control frame destined for address FF-FF-FF-FF-FF-FFh only • Was of any length • Had no late or excessive collisions, no carrier loss, and no underrun 5.50.
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EMAC Port Registers www.ti.com • • • Was any size Had no carrier loss and no underrun Experienced one collision before successful transmission. The collision was not late. CRC errors have no effect on this statistic. 5.50.21 Transmit Multiple Collision Frames Register (TXMULTICOLL) The total number of frames transmitted on the EMAC that experienced multiple collisions.
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EMAC Port Registers www.ti.com 5.50.25 Transmit Carrier Sense Errors Register (TXCARRIERSENSE) The total number of frames on the EMAC that experienced carrier loss. Such a frame is defined as having all of the following: • Was any data or MAC control frame destined for any unicast, broadcast, or multicast address • Was any size • The carrier sense condition was lost or never asserted when transmitting the frame (the frame is not re-transmitted) CRC errors and underrun have no effect on this statistic. 5.
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EMAC Port Registers www.ti.com 5.50.30 Transmit and Receive 256 to 511 Octet Frames Register (FRAME256T511) The total number of 256-byte to 511-byte frames received and transmitted on the EMAC.
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EMAC Port Registers www.ti.com 5.50.34 Receive FIFO or DMA Start-of-Frame Overruns Register (RXSOFOVERRUNS) The total number of frames received on the EMAC that had either a FIFO or DMA start-of-frame (SOF) overrun.
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www.ti.com Appendix A Glossary Broadcast MAC Address— A special Ethernet MAC address used to send data to all Ethernet devices on the local network. The broadcast address is FFh-FFh-FFh-FFh-FFh-FFh. The LSB of the first byte is odd, qualifying it as a group address; however, its value is reserved for broadcast. It is classified separately by the EMAC. Descriptor (Packet Buffer Descriptor)— A small memory structure that describes a larger block of memory in terms of size, location, and state.
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Appendix A www.ti.com Jumbo Packets— Jumbo frames are defined as those packets whose length exceeds the standard Ethernet MTU, which is 1500 kbytes. For the C64x+ devices, it is recommended not to use packets exceeding 35K in length. The PHY that you use can place additional limits on to the length of the packets that you can transfer in a system. Link— The transmission path between any two instances of generic cabling.
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www.ti.com Appendix B Revision History This revision history highlights the technical changes made to the document in this revision. Table 87.
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