Datasheet

TMS320F28335, TMS320F28334, TMS320F28332

TMS320F28235, TMS320F28234, TMS320F28232

www.ti.com

SPRS439M –JUNE 2007–REVISED AUGUST 2012

Table 3-19. Possible PLL Configuration Modes

CLKIN AND

PLL MODE REMARKS PLLSTS[DIVSEL]

SYSCLKOUT

Invoked by the user setting the PLLOFF bit in the PLLSTS register. The PLL block

is disabled in this mode. This can be useful to reduce system noise and for low 0, 1 OSCCLK/4

PLL Off power operation. The PLLCR register must first be set to 0x0000 (PLL Bypass) 2 OSCCLK/2

before entering this mode. The CPU clock (CLKIN) is derived directly from the 3 OSCCLK/1

input clock on either X1/X2, X1 or XCLKIN.

PLL Bypass is the default PLL configuration upon power-up or after an external

0, 1 OSCCLK/4

reset (XRS). This mode is selected when the PLLCR register is set to 0x0000 or

PLL Bypass 2 OSCCLK/2

while the PLL locks to a new frequency after the PLLCR register has been

3 OSCCLK/1

modified. In this mode, the PLL itself is bypassed but the PLL is not turned off.

Achieved by writing a non-zero value n into the PLLCR register. Upon writing to the 0, 1 OSCCLK*n/4

PLL Enable

PLLCR the device will switch to PLL Bypass mode until the PLL locks. 2 OSCCLK*n/2

3.6.1.3 Loss of Input Clock

In PLL-enabled and PLL-bypass mode, if the input clock OSCCLK is removed or absent, the PLL will still

issue a limp-mode clock. The limp-mode clock continues to clock the CPU and peripherals at a typical

frequency of 1–5 MHz. Limp mode is not specified to work from power-up, only after input clocks have

been present initially. In PLL bypass mode, the limp mode clock from the PLL is automatically routed to

the CPU if the input clock is removed or absent.

Normally, when the input clocks are present, the watchdog counter decrements to initiate a watchdog

reset or WDINT interrupt. However, when the external input clock fails, the watchdog counter stops

decrementing (that is, the watchdog counter does not change with the limp-mode clock). In addition to

this, the device will be reset and the “Missing Clock Status” (MCLKSTS) bit will be set. These conditions

could be used by the application firmware to detect the input clock failure and initiate necessary shut-down

procedure for the system.

NOTE

Applications in which the correct CPU operating frequency is absolutely critical should

implement a mechanism by which the DSC will be held in reset, should the input clocks ever

fail. For example, an R-C circuit may be used to trigger the XRS pin of the DSC, should the

capacitor ever get fully charged. An I/O pin may be used to discharge the capacitor on a

periodic basis to prevent it from getting fully charged. Such a circuit would also help in

detecting failure of the flash memory and the V

DD3VFL

rail.

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