Datasheet

TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
SPRS439M –JUNE 2007–REVISED AUGUST 2012 www.ti.com
6.4 Current Consumption
Table 6-1. TMS320F28335/F28235 Current Consumption by Power-Supply Pins at 150-MHz SYSCLKOUT
I
DD
I
DDIO
(1)
I
DD3VFL
(2)
I
DDA18
(3)
I
DDA33
(4)
MODE TEST CONDITIONS
TYP
(5)
MAX TYP
(5)
MAX TYP MAX TYP
(5)
MAX TYP
(5)
MAX
The following peripheral clocks
are enabled:
• ePWM1, ePWM2,
ePWM3, ePWM4,
ePWM5, ePWM6
• eCAP1, eCAP2, eCAP3,
eCAP4, eCAP5, eCAP6
• eQEP1, eQEP2
• eCAN-A
• SCI-A, SCI-B
Operational
290 mA 315 mA 30 mA 50 mA 35 mA 40 mA 30 mA 35 mA 1.5 mA 2 mA
(FIFO mode)
(Flash)
(6)
• SPI-A (FIFO mode)
• ADC
• I2C
• CPU-Timer 0,
CPU-Timer 1,
CPU-Timer 2
All PWM pins are toggled at
150 kHz.
All I/O pins are left
unconnected.
(7)
Flash is powered down.
XCLKOUT is turned off.
The following peripheral clocks
are enabled:
IDLE 100 mA 120 mA 60 μA 120 μA 2 μA 10 μA 5 μA 60 μA 15 μA 20 μA
• eCAN-A
• SCI-A
• SPI-A
• I2C
Flash is powered down.
STANDBY 8 mA 15 mA 60 μA 120 μA 2 μA 10 μA 5 μA 60 μA 15 μA 20 μA
Peripheral clocks are off.
Flash is powered down.
HALT
(8)
Peripheral clocks are off. 150 μA 60 μA 120 μA 2 μA 10 μA 5 μA 60 μA 15 μA 20 μA
Input clock is disabled.
(9)
(1) I
DDIO
current is dependent on the electrical loading on the I/O pins.
(2) The I
DD3VFL
current indicated in this table is the flash read-current and does not include additional current for erase/write operations.
During flash programming, extra current is drawn from the V
DD
and V
DD3VFL
rails, as indicated in Table 6-67. If the user application
involves on-board flash programming, this extra current must be taken into account while architecting the power-supply stage.
(3) I
DDA18
includes current into V
DD1A18
and V
DD2A18
pins. In order to realize the I
DDA18
currents shown for IDLE, STANDBY, and HALT,
clock to the ADC module must be turned off explicitly by writing to the PCLKCR0 register.
(4) I
DDA33
includes current into V
DDA2
and V
DDAIO
pins.
(5) The TYP numbers are applicable over room temperature and nominal voltage. MAX numbers are at 125°C, and MAX voltage (V
DD
=
2.0 V; V
DDIO
, V
DD3VFL
, V
DDA
= 3.6 V).
(6) When the identical code is run off SARAM, I
DD
would increase as the code operates with zero wait states.
(7) The following is done in a loop:
• Data is continuously transmitted out of the SCI-A, SCI-B, SPI-A, McBSP-A, and eCAN-A ports.
• Multiplication/addition operations are performed.
• Watchdog is reset.
• ADC is performing continuous conversion. Data from ADC is transferred to SARAM through the DMA.
• 32-bit read/write of the XINTF is performed.
• GPIO19 is toggled.
(8) HALT mode I
DD
currents will increase with temperature in a non-linear fashion.
(9) If a quartz crystal or ceramic resonator is used as the clock source, the HALT mode shuts down the internal oscillator.
NOTE
The peripheral - I/O multiplexing implemented in the device prevents all available peripherals
from being used at the same time. This is because more than one peripheral function may
share an I/O pin. It is, however, possible to turn on the clocks to all the peripherals at the
same time, although such a configuration is not useful. If this is done, the current drawn by
the device will be more than the numbers specified in the current consumption tables.
118 Electrical Specifications Copyright © 2007–2012, Texas Instruments Incorporated
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