Datasheet

ADC
RESULT
registers
ADC
CPU
PF0
I/F
ADC
DMA
PF0
I/F
ADC
control
and
RESULT
registers
ADC
PF2
I/F
L4
I/F
L4
SARAM
(4Kx16)
L5
I/F
L5
SARAM
(4Kx16)
L6
I/F
L6
SARAM
(4Kx16)
L7
I/F
L7
SARAM
(4Kx16)
PF3
I/F
McBSP A
McBSP B
Event
triggers
DMA
6-ch
External
interrupts
CPU
timers
CPUbus
DMA bus
PIE
INT7
DINT[CH1:CH6]
CPU
XINTFzonesinterface
XINTFmemoryzones
ePWM/
HRPWM
registers
(A)
TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
www.ti.com SPRS439M –JUNE 2007–REVISED AUGUST 2012
A. The ePWM and HRPWM registers must be remapped to PF3 (through bit 0 of the MAPCNF register) before they can
be accessed by the DMA. The ePWM or HRPWM connection to DMA is not present in silicon revision 0.
Figure 4-1. DMA Functional Block Diagram
Copyright © 2007–2012, Texas Instruments Incorporated Peripherals 65
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TMS320F28232