Datasheet

Lead 1
Active
Trail
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
XA[0:19]
t
d(XCOHL-XWEH)
t
d(XCOHL-XZCSH)
t
d(XCOH-XA)
WS (Async)
XZCS0
, XZCS6, XZCS7
XRD
XWE0, XWE1
(D)
XR/W
t
d(XCOH-XZCSL)
t
d(XCOH-XRNWL)
t
d(XCOHL-XRNWH)
t
en(XD)XWEL
t
h(XD)XWEH
t
h(XRDYasynchL)
DOUT
t
dis(XD)XRNW
t
h(XRDYasynchH)XZCSH
(E)
(D)
= Don’t care. Signal can be high or low during this time.
Legend:
t
su(XRDYasynchL)XCOHL
t
su(XRDYasynchH)XCOHL
t
d(XWEL-XD
)
t
d(XCOHL-XWEL)
(A) (B)
(C)
t
e(XRDYasynchH)
XREADY(Asynch)
XD[31:0], XD[15:0]
TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
www.ti.com SPRS439M –JUNE 2007–REVISED AUGUST 2012
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an
alignment cycle before an access to meet this requirement.
B. During alignment cycles, all signals transition to their inactive state.
C. During inactive cycles, the XINTF address bus always holds the last address put out on the bus except XA0, which
remains high. This includes alignment cycles.
D. XWE1 is used in 32-bit data bus mode only. In 16-bit, this signal is XA0.
E. For each sample, set up time from the beginning of the access can be calculated as: E = (XWRLEAD + XWRACTIVE
-3 + n) t
c(XTIM)
– t
su(XRDYasynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
F. Reference for the first sample is with respect to this point: F = (XWRLEAD + XWRACTIVE – 2) t
c(XTIM)
Figure 6-28. Write With Asynchronous XREADY Access
XTIMING register parameters used for this example:
XRDLEAD XRDACTIVE XRDTRAIL USEREADY X2TIMING XWRLEAD XWRACTIVE XWRTRAIL READYMODE
N/A
(1)
N/A
(1)
N/A
(1)
1 0 ≥ 1 3 ≥ 1 1 = XREADY
(Async)
(1) N/A = “Don’t care” for this example
Copyright © 2007–2012, Texas Instruments Incorporated Electrical Specifications 165
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