Datasheet

PWM
(B)
TZ
(A)
SYSCLK
t
w(TZ)
t
d(TZ-PWM)HZ
TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
www.ti.com SPRS439M –JUNE 2007–REVISED AUGUST 2012
6.10 Enhanced Control Peripherals
6.10.1 Enhanced Pulse Width Modulator (ePWM) Timing
PWM refers to PWM outputs on ePWM1–6. Table 6-20 shows the PWM timing requirements and Table 6-
21, switching characteristics.
Table 6-20. ePWM Timing Requirements
(1)
TEST CONDITIONS MIN MAX UNIT
t
w(SYCIN)
Sync input pulse width Asynchronous 2t
c(SCO)
cycles
Synchronous 2t
c(SCO)
cycles
With input qualifier 1t
c(SCO)
+ t
w(IQSW)
cycles
(1) For an explanation of the input qualifier parameters, see Table 6-13.
Table 6-21. ePWM Switching Characteristics
PARAMETER TEST CONDITIONS MIN MAX UNIT
t
w(PWM)
Pulse duration, PWMx output high/low 20 ns
t
w(SYNCOUT)
Sync output pulse width 8t
c(SCO)
cycles
t
d(PWM)tza
Delay time, trip input active to PWM forced high no pin load 25 ns
Delay time, trip input active to PWM forced low
t
d(TZ-PWM)HZ
Delay time, trip input active to PWM Hi-Z 20 ns
6.10.2 Trip-Zone Input Timing
A. TZ - TZ1, TZ2, TZ3, TZ4, TZ5, TZ6
B. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM
recovery software.
Figure 6-15. PWM Hi-Z Characteristics
Table 6-22. Trip-Zone Input Timing Requirements
(1)
MIN MAX UNIT
t
w(TZ)
Pulse duration, TZx input low Asynchronous 1t
c(SCO)
cycles
Synchronous 2t
c(SCO)
cycles
With input qualifier 1t
c(SCO)
+ t
w(IQSW)
cycles
(1) For an explanation of the input qualifier parameters, see Table 6-13.
Copyright © 2007–2012, Texas Instruments Incorporated Electrical Specifications 139
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