Datasheet

WDINT
LPMINT
Watchdog
Low-PowerModels
Sync
SYSCLKOUT
WAKEINT
DMA
Clear
Peripherals
(SPI,SCI,I2C,CAN,McBSP
C )
(A)
,
ePWM ,eCAP,eQEP, AD
(A) (A)
DMA
XINT1
InterruptControl
XINT1CR(15:0)
XINT1CTR(15:0)
XINT1
Latch
MUX
GPIOXINT1SEL(4:0)
DMA
XINT2
InterruptControl
XINT2CR(15:0)
XINT2CTR(15:0)
XINT2
Latch
MUX
GPIOXINT2SEL(4:0)
ADC
XINT2SOC
DMA
TINT0
CPUTimer0
DMA
TINT2
CPUTimer2
CPUTimer1
MUX
TINT1
InterruptControl
XNMICR(15:0)
XNMICTR(15:0)
MUX
1
DMA
NMI
INT13
INT14
INT1
to
INT12
C28
Core
96Interrupts
PIE
XNMI_
XINT13
Latch
MUX
GPIOXNMISEL(4:0)
GPIO
Mux
GPIO0.int
GPIO31.int
TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
SPRS439M –JUNE 2007–REVISED AUGUST 2012 www.ti.com
3.5 Interrupts
Figure 3-5 shows how the various interrupt sources are multiplexed.
A. DMA-accessible
Figure 3-5. External and PIE Interrupt Sources
52 Functional Overview Copyright © 2007–2012, Texas Instruments Incorporated
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TMS320F28232