Datasheet

TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
SPRS174T –APRIL 2001–REVISED MAY 2012 www.ti.com
Table 2-2. Signal Descriptions
(1)
(continued)
PIN NO.
NAME I/O/Z
(2)
PU/PD
(3)
DESCRIPTION
179-BALL 176-PIN 128-PIN
GHH/ZHH PGF PBK
Microprocessor/Microcomputer Mode Select.
Switches between microprocessor and
microcomputer mode. When high, Zone 7 is
enabled on the external interface. When low,
Zone 7 is disabled from the external interface,
XMP/MC F1 17 – I PD
and on-chip boot ROM may be accessed
instead. This signal is latched into the
XINTCNF2 register on a reset and the user
can modify this bit in software. The state of the
XMP/MC pin is ignored after reset.
External Hold Request. XHOLD, when active
(low), requests the XINTF to release the
external bus and place all buses and strobes
XHOLD E7 159 – I PU into a high-impedance state. The XINTF will
release the bus when any current access is
complete and there are no pending accesses
on the XINTF.
External Hold Acknowledge. XHOLDA is
driven active (low) when the XINTF has
granted a XHOLD request. All XINTF buses
and strobe signals will be in a high-impedance
XHOLDA K10 82 – O/Z –
state. XHOLDA is released when the XHOLD
signal is released. External devices should
only drive the external bus when XHOLDA is
active (low).
XINTF Zone 0 and Zone 1 Chip Select.
XZCS0AND1 P1 44 – O/Z – XZCS0AND1 is active (low) when an access
to the XINTF Zone 0 or Zone 1 is performed.
XINTF Zone 2 Chip Select. XZCS2 is active
XZCS2 P13 88 – O/Z – (low) when an access to the XINTF Zone 2 is
performed.
XINTF Zone 6 and Zone 7 Chip Select.
XZCS6AND7 B13 133 – O/Z – XZCS6AND7 is active (low) when an access
to the XINTF Zone 6 or Zone 7 is performed.
Write Enable. Active-low write strobe. The
write strobe waveform is specified, per zone
XWE N11 84 – O/Z –
basis, by the Lead, Active, and Trail periods in
the XTIMINGx registers.
Read Enable. Active-low read strobe. The
read strobe waveform is specified, per zone
XRD M3 42 – O/Z – basis, by the Lead, Active, and Trail periods in
the XTIMINGx registers. NOTE: The XRD and
XWE signals are mutually exclusive.
Read Not Write Strobe. Normally held high.
When low, XR/W indicates write cycle is
XR/W N4 51 – O/Z –
active; when high, XR/W indicates read cycle
is active.
Ready Signal. Indicates peripheral is ready to
complete the access when asserted to 1.
XREADY B6 161 – I PU XREADY can be configured to be a
synchronous or an asynchronous input. See
the timing diagrams for more details.
18 Introduction Copyright © 2001–2012, Texas Instruments Incorporated
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