Datasheet

XCLKOUT
(1/2 XTIMCLK)
XHOLD
XR/ ,
,
,
W
XZCS0AND1
XZCS2
XZCS6AND7
XD[15:0]
Valid
XHOLDA
t
d(HL-HiZ)
t
d(HH-HAH)
High-Impedance
High-Impedance
High-Impedance
XA[18:0]
Valid Valid
t
d(HH-BV)
t
d(HL-HAL)
See Note (A)
See Note (B)
TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
SPRS174T –APRIL 2001–REVISED MAY 2012 www.ti.com
Table 6-43. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)
(1)(2)(3)
MIN MAX UNIT
t
d(HL-HiZ)
Delay time, XHOLD low to Hi-Z on all Address, Data, and Control 4t
c(XTIM)
+ t
c(XCO)
ns
t
d(HL-HAL)
Delay time, XHOLD low to XHOLDA low 4t
c(XTIM)
+ 2t
c(XCO)
ns
t
d(HH-HAH)
Delay time, XHOLD high to XHOLDA high 4t
c(XTIM)
ns
t
d(HH-BV)
Delay time, XHOLD high to Bus valid 6t
c(XTIM)
ns
(1) When a low signal is detected on XHOLD, all pending XINTF accesses will be completed before the bus is placed in a high-impedance
state.
(2) The state of XHOLD is latched on the rising edge of XTIMCLK.
(3) After the XHOLD is detected low or high, all bus transitions and XHOLDA transitions will occur with respect to the rising edge of
XCLKOUT. Thus, for this mode where XCLKOUT = 1/2 XTIMCLK, the transitions can occur up to 1 XTIMCLK cycle earlier than the
maximum value specified.
A. All pending XINTF accesses are completed.
B. Normal XINTF operation resumes.
Figure 6-38. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)
142 Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated
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