Datasheet

Only one of these vector maps - M0 vector, PIE vector, BROM vector - should be enabled at a time.
LEGEND:
Block
Start Address
Low 64K
(24x/240x Equivalent Data Space)
High 64K
(24x/240x Equivalent
Program Space)
0x00 0000
M0 Vector - RAM (32 x 32)
(Enabled if VMAP = 0)
×
BROM Vector - ROM (32 x 32)
(Enabled if VMAP = 1, MP/ = 0, ENPIE = 0)MC
×
Data Space
Prog Space
M0 SARAM (1K x 16)
M1 SARAM (1K x 16)
×
Peripheral Frame 0
0x00 0040
0x00 0400
0x00 0800
PIE Vector - RAM
(256 x 16)
(Enabled if
VMAP = 1, ENPIE = 1)
L0 SARAM (4K x 16, Secure Block)
Peripheral Frame 1
(Protected)
Peripheral Frame 2
(Protected)
L1 SARAM (4K x 16, Secure Block)
×
OTP (or ROM) (1K x 16, Secure Block)
Flash (or ROM) (128K x 16, Secure Block)
128-Bit Password
H0 SARAM (8K x 16)
Boot ROM (4K x 16)
(Enabled if MP/ = 0)MC
0x00 0D00
0x00 0E00
0x00 2000
0x00 6000
0x00 7000
0x00 8000
0x00 9000
0x00 A000
0x3D 7800
0x3D 7C00
0x3F 7FF8
0x3F 8000
0x3F A000
0x3F F000
0x3F FFC0
On-Chip Memory
0x3D 8000
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved (1K)
Reserved
TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
SPRS174T –APRIL 2001–REVISED MAY 2012 www.ti.com
A. Memory blocks are not to scale.
B. Reserved locations are reserved for future expansion. Application should not access these areas.
C. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only.
User program cannot access these memory maps in program space.
D. “Protected” means the order of Write followed by Read operations is preserved rather than the pipeline order.
E. Certain memory ranges are EALLOW protected against spurious writes after configuration.
Figure 3-3. F2811/C2811 Memory Map
28 Functional Overview Copyright © 2001–2012, Texas Instruments Incorporated
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Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812