Datasheet

TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
SPRS174T –APRIL 2001–REVISED MAY 2012 www.ti.com
6.26 External Interface Ready-on-Read Timing With One External Wait State
Table 6-35. External Memory Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State)
PARAMETER MIN MAX UNIT
t
d(XCOH-XZCSL)
Delay time, XCLKOUT high to zone chip-select active-low 1 ns
t
d(XCOHL-XZCSH)
Delay time, XCLKOUT high/low to zone chip-select inactive-high –2 3 ns
t
d(XCOH-XA)
Delay time, XCLKOUT high to address valid 2 ns
t
d(XCOHL-XRDL)
Delay time, XCLKOUT high/low to XRD active-low 1 ns
t
d(XCOHL-XRDH)
Delay time, XCLKOUT high/low to XRD inactive-high –2 1 ns
t
h(XA)XZCSH
Hold time, address valid after zone chip-select inactive-high
(1)
ns
t
h(XA)XRD
Hold time, address valid after XRD inactive-high
(1)
ns
(1) During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.
Table 6-36. External Memory Interface Read Timing Requirements (Ready-on-Read, 1 Wait State)
MIN MAX UNIT
t
a(A)
Access time, read data from address valid (LR + AR) – 14
(1)
ns
t
a(XRD)
Access time, read data valid from XRD active-low AR – 12
(1)
ns
t
su(XD)XRD
Setup time, read data valid before XRD strobe inactive-high 12 ns
t
h(XD)XRD
Hold time, read data valid after XRD inactive-high 0 ns
(1) LR = Lead period, read access. AR = Active period, read access. See Table 6-30.
Table 6-37. Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)
(1)
MIN MAX UNIT
t
su(XRDYsynchL)XCOHL
Setup time, XREADY (synchronous) low before XCLKOUT high/low 15 ns
t
h(XRDYsynchL)
Hold time, XREADY (synchronous) low 12 ns
Earliest time XREADY (synchronous) can go high before the sampling
t
e(XRDYsynchH)
3 ns
XCLKOUT edge
t
su(XRDYsynchH)XCOHL
Setup time, XREADY (synchronous) high before XCLKOUT high/low 15 ns
t
h(XRDYsynchH)XZCSH
Hold time, XREADY (synchronous) held high after zone chip-select high 0 ns
(1) The first XREADY (synchronous) sample occurs with respect to E in Figure 6-33:
E = (XRDLEAD + XRDACTIVE) t
c(XTIM)
When first sampled, if XREADY (synchronous) is found to be high, then the access will complete. If XREADY (synchronous) is found to
be low, it will be sampled again each t
c(XTIM)
until it is found to be high.
For each sample (n), the setup time (D) with respect to the beginning of the access can be calculated as:
D = (XRDLEAD + XRDACTIVE + n – 1) t
c(XTIM)
– t
su(XRDYsynchL)XCOHL
where n is the sample number (n = 1, 2, 3, and so forth).
Table 6-38. Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)
(1)
MIN MAX UNIT
t
su(XRDYAsynchL)XCOHL
Setup time, XREADY (asynchronous) low before XCLKOUT high/low 11 ns
t
h(XRDYAsynchL)
Hold time, XREADY (asynchronous) low 8 ns
Earliest time XREADY (asynchronous) can go high before the sampling
t
e(XRDYAsynchH)
3 ns
XCLKOUT edge
t
su(XRDYAsynchH)XCOHL
Setup time, XREADY (asynchronous) high before XCLKOUT high/low 11 ns
t
h(XRDYAsynchH)XZCSH
Hold time, XREADY (asynchronous) held high after zone chip-select high 0 ns
(1) The first XREADY (asynchronous) sample occurs with respect to E in Figure 6-34:
E = (XRDLEAD + XRDACTIVE – 2) t
c(XTIM)
When first sampled, if XREADY (asynchronous) is found to be high, then the access will complete. If XREADY (asynchronous) is found
to be low, it will be sampled again each t
c(XTIM)
until it is found to be high.
For each sample, setup time from the beginning of the access can be calculated as:
D = (XRDLEAD + XRDACTIVE – 3 + n) t
c(XTIM)
– t
su(XRDYAsynchL)XCOHL
where n is the sample number (n = 1, 2, 3, and so forth).
134 Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated
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