Datasheet
TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
SPRS174T –APRIL 2001–REVISED MAY 2012
www.ti.com
Table 6-26. SPI Master Mode External Timing (Clock Phase = 0)
(1)(2)
SPI WHEN (SPIBRR + 1) IS EVEN OR SPI WHEN (SPIBRR + 1) IS ODD AND
SPIBRR = 0 OR 2 SPIBRR > 3
NO. UNIT
MIN MAX MIN MAX
1 t
c(SPC)M
Cycle time, SPICLK 4t
c(LCO)
128t
c(LCO)
5t
c(LCO)
127t
c(LCO)
ns
t
w(SPCH)M
Pulse duration, SPICLK high 0.5t
c(SPC)M
– 10 0.5t
c(SPC)M
0.5t
c(SPC)M
– 0.5t
c(LCO)
– 10 0.5t
c(SPC)M
– 0.5t
c(LCO)
(clock polarity = 0)
2
(3)
ns
t
w(SPCL)M
Pulse duration, SPICLK low 0.5t
c(SPC)M
– 10 0.5t
c(SPC)M
0.5t
c(SPC)M
– 0.5t
c(LCO)
– 10 0.5t
c(SPC)M
– 0.5t
c(LCO)
(clock polarity = 1)
t
w(SPCL)M
Pulse duration, SPICLK low 0.5t
c(SPC)M
– 10 0.5t
c(SPC)M
0.5t
c(SPC)M
+ 0.5t
c(LCO)
– 10 0.5t
c(SPC)M
+ 0.5t
c(LCO)
(clock polarity = 0)
3
(3)
ns
t
w(SPCH)M
Pulse duration, SPICLK high 0.5t
c(SPC)M
– 10 0.5t
c(SPC)M
0.5t
c(SPC)M
+ 0.5t
c(LCO)
– 10 0.5t
c(SPC)M
+ 0.5t
c(LCO)
(clock polarity = 1)
t
d(SPCH-SIMO)M
Delay time, SPICLK high to SPISIMO –10 10 –10 10
valid (clock polarity = 0)
4
(3)
ns
t
d(SPCL-SIMO)M
Delay time, SPICLK low to SPISIMO –10 10 –10 10
valid (clock polarity = 1)
t
v(SPCL-SIMO)M
Valid time, SPISIMO data valid after 0.5t
c(SPC)M
– 10 0.5t
c(SPC)M
+ 0.5t
c(LCO)
– 10
SPICLK low (clock polarity = 0)
5
(3)
ns
t
v(SPCH-SIMO)M
Valid time, SPISIMO data valid after 0.5t
c(SPC)M
– 10 0.5t
c(SPC)M
+ 0.5t
c(LCO)
– 10
SPICLK high (clock polarity = 1)
t
su(SOMI-SPCL)M
Setup time, SPISOMI before SPICLK 0 0
low (clock polarity = 0)
8
(3)
ns
t
su(SOMI-SPCH)M
Setup time, SPISOMI before SPICLK 0 0
high (clock polarity = 1)
t
v(SPCL-SOMI)M
Valid time, SPISOMI data valid after 0.25t
c(SPC)M
– 10 0.5t
c(SPC)M
– 0.5t
c(LCO)
– 10
SPICLK low (clock polarity = 0)
9
(3)
ns
t
v(SPCH-SOMI)M
Valid time, SPISOMI data valid after 0.25t
c(SPC)M
– 10 0.5t
c(SPC)M
– 0.5t
c(LCO)
– 10
SPICLK high (clock polarity = 1)
(1) The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) t
c(SPC)
= SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
t
c(LCO)
= LSPCLK cycle time
(3) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
NOTE: Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
• Master mode transmit: 20 MHz MAX. Master mode receive: 12.5 MHz MAX.
• Slave mode transmit: 12.5 MHz MAX. Slave mode receive: 12.5 MHz MAX.
118 Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated
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