Datasheet

PLL
X1
X2
Power
Modes
Control
Watchdog
Block
28x
CPU
Peripheral Bus
High-Speed Prescaler
Low-Speed Prescaler
Clock Enables
GPIO
MUX
XCLKIN
16 ADC Inputs
LSPCLK
I/O
Peripheral Reset
SYSCLKOUT
(A)
XRS
Reset
GPIOs
I/O
OSC
CLKIN
(A)
HSPCLK
I/O
Peripheral
Registers
CPU
Timers
System
Control
Registers
Peripheral
Registers
ePWM 1/2/3/4/5/6
eCAP 1/2/3/4 eQEP 1/2
ADC
Registers
12-Bit ADC
Peripheral
Registers
Low-Speed Peripherals
SCI-A/B, SPI-A/B/C/D
Peripheral
Registers
eCAN-A/B
I2C-A
TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015
www.ti.com SPRS230N –OCTOBER 2003–REVISED MAY 2012
Each external interrupt can be enabled/disabled or qualified using positive, negative, or both positive and
negative edge. For more information, see the TMS320x280x, 2801x, 2804x DSP System Control and
Interrupts Reference Guide (literature number SPRU712).
3.6 System Control
This section describes the 280x oscillator, PLL and clocking mechanisms, the watchdog function and the
low power modes. Figure 3-9 shows the various clock and reset domains in the 280x devices that will be
discussed.
A. CLKIN is the clock into the CPU. It is passed out of the CPU as SYSCLKOUT (that is, CLKIN is the same frequency
as SYSCLKOUT).
Figure 3-9. Clock and Reset Domains
Copyright © 2003–2012, Texas Instruments Incorporated Functional Overview 45
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TMS320C2801 TMS320F28016 TMS320F28015