Datasheet

CLA_INT1 to CLA_INT8
MVECT1
MVECT2
MPERINT1
to
MPERINT8
PIE
Main
28x
CPU
CLA
Program
Memory
MMEMCFG
MCTL
MIFR
MIER
MIFRC
MIRUN
MIOVF
MICLR
MICLROVF
MPISRCSEL1
MVECT3
MVECT4
MVECT5
MVECT6
MVECT7
MVECT8
ain CPU BUS
INT11
INT12
Peripheral Interrupts
ADCINT1 to ADCINT8
ECAP1_INT to ECAP3_INT
EQEP1_INT and EQEP2_INT
EPWM1_INT to EPWM8_INT
CPU Timer 0
Map to CLA or
CPU Space
CLA
Data
Memory
Comparator
Registers
eCAP
Registers
eQEP
Registers
ePWM
and
HRPWM
Registers
ADC
Result
Registers
CLA
Shared
Message
RAMs
Main CPU Read/Write Data Bus
CLA Program Address Bus
CLA Program Data Bus
Map to CLA or
CPU Space
CLA Data Bus
Main CPU Bus
MR0(32)
MPC(12)
MR1(32)
MR3(32)
MAR0(32)
MSTF(32)
MR2(32)
MAR1(32)
CLA Data Read Address Bus
CLA Data Write Data Bus
CLA Data Write Address Bus
CLA Data Read Data Bus
MEALLOW
Main CPU Read Data Bus
CLA Execution
Registers
CLA Control
Registers
SYSCLKOUT
CLAENCLK
SYSRS
LVF
LUF
IACK
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
SPRS698D –NOVEMBER 2010–REVISED DECEMBER 2012 www.ti.com
Figure 5-13. CLA Block Diagram
80 Peripheral and Electrical Specifications Copyright © 2010–2012, Texas Instruments Incorporated
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TMS320F28064 TMS320F28063 TMS320F28062