Datasheet

TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
SPRS698D –NOVEMBER 2010–REVISED DECEMBER 2012 www.ti.com
Table 5-66. GPIOB MUX
(1)(2)
DEFAULT AT RESET PERIPHERAL PERIPHERAL PERIPHERAL
PRIMARY I/O FUNCTION SELECTION 1 SELECTION 2 SELECTION 3
GPBMUX1 REGISTER
(GPBMUX1 BITS = 00) (GPBMUX1 BITS = 01) (GPBMUX1 BITS = 10) (GPBMUX1 BITS = 11)
BITS
1-0 GPIO32 SDAA (I/OD) EPWMSYNCI (I) ADCSOCAO (O)
3-2 GPIO33 SCLA (I/OD) EPWMSYNCO (O) ADCSOCBO (O)
5-4 GPIO34 COMP2OUT (O) Reserved COMP3OUT (O)
7-6 GPIO35 (TDI) Reserved Reserved Reserved
9-8 GPIO36 (TMS) Reserved Reserved Reserved
11-10 GPIO37 (TDO) Reserved Reserved Reserved
13-12 GPIO38/XCLKIN (TCK) Reserved Reserved Reserved
15-14 GPIO39 Reserved Reserved Reserved
17-16 GPIO40
(3)
EPWM7A (O) SCITXDB (O) Reserved
19-18 GPIO41
(3)
EPWM7B (O) SCIRXDB (I) Reserved
21-20 GPIO42
(3)
EPWM8A (O) TZ1 (I) COMP1OUT (O)
23-22 GPIO43
(3)
EPWM8B (O) TZ2 (I) COMP2OUT (O)
25-24 GPIO44
(3)
MFSRA (I/O) SCIRXDB (I) EPWM7B (O)
27-26 Reserved Reserved Reserved Reserved
29-28 Reserved Reserved Reserved Reserved
31-30 Reserved Reserved Reserved Reserved
GPBMUX2 REGISTER
(GPBMUX2 BITS = 00) (GPBMUX2 BITS = 01) (GPBMUX2 BITS = 10) (GPBMUX2 BITS = 11)
BITS
1-0 Reserved Reserved Reserved Reserved
3-2 Reserved Reserved Reserved Reserved
5-4 GPIO50
(3)
EQEP1A (I) MDXA (O) TZ1 (I)
7-6 GPIO51
(3)
EQEP1B (I) MDRA (I) TZ2 (I)
9-8 GPIO52
(3)
EQEP1S (I/O) MCLKXA (I/O) TZ3 (I)
11-10 GPIO53
(3)
EQEP1I (I/O) MFSXA (I/O) Reserved
13-12 GPIO54
(3)
SPISIMOA (I/O) EQEP2A (I) HRCAP1 (I)
15-14 GPIO55
(3)
SPISOMIA (I/O) EQEP2B (I) HRCAP2 (I)
17-16 GPIO56
(3)
SPICLKA (I/O) EQEP2I (I/O) HRCAP3 (I)
19-18 GPIO57
(3)
SPISTEA (I/O) EQEP2S (I/O) HRCAP4 (I)
21-20 GPIO58
(3)
MCLKRA (I/O) SCITXDB (O) EPWM7A (O)
23-22 Reserved Reserved Reserved Reserved
25-24 Reserved Reserved Reserved Reserved
27-26 Reserved Reserved Reserved Reserved
29-28 Reserved Reserved Reserved Reserved
31-30 Reserved Reserved Reserved Reserved
(1) The word "Reserved" means that there is no peripheral assigned to this GPxMUX1/2 register setting. Should it be selected, the state of
the pin will be undefined and the pin may be driven. This selection is a reserved configuration for future expansion.
(2) I = Input, O = Output, OD = Open Drain
(3) This pin is not available in the 80-pin PN or PFP package.
144 Peripheral and Electrical Specifications Copyright © 2010–2012, Texas Instruments Incorporated
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TMS320F28064 TMS320F28063 TMS320F28062