Datasheet

TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
www.ti.com SPRS698D –NOVEMBER 2010–REVISED DECEMBER 2012
5.3 Device Clock Table
This section provides the timing requirements and switching characteristics for the various clock options
available on the 2806x MCUs. Table 5-1 lists the cycle times of various clocks.
Table 5-1. 2806x Clock Table and Nomenclature (90-MHz Devices)
MIN NOM MAX UNIT
t
c(SCO)
, Cycle time 11.11 500 ns
SYSCLKOUT
Frequency 2 90 MHz
t
c(LCO)
, Cycle time 11.11 44.4
(2)
ns
LSPCLK
(1)
Frequency 22.5
(2)
90 MHz
t
c(ADCCLK)
, Cycle time 22.22 ns
ADC clock
Frequency 45 MHz
(1) Lower LSPCLK will reduce device power consumption.
(2) This is the default reset value if SYSCLKOUT = 90 MHz.
Table 5-2. Device Clocking Requirements/Characteristics
MIN NOM MAX UNIT
t
c(OSC)
, Cycle time 50 200 ns
On-chip oscillator (X1/X2 pins)
(Crystal/Resonator)
Frequency 5 20 MHz
t
c(CI)
, Cycle time (C8) 33.3 200 ns
External oscillator/clock source
(XCLKIN pin) — PLL Enabled
Frequency 5 30 MHz
t
c(CI)
, Cycle time (C8) 11.11 250 ns
External oscillator/clock source
(XCLKIN pin) — PLL Disabled
Frequency 4 90 MHz
Limp mode SYSCLKOUT
Frequency range 1 to 5 MHz
(with /2 enabled)
t
c(XCO)
, Cycle time (C1) 50 2000 ns
XCLKOUT
Frequency 0.5 20 MHz
PLL lock time
(1)
t
p
1 ms
(1) The PLLLOCKPRD register must be updated based on the number of OSCCLK cycles. If the zero-pin internal oscillators (10 MHz) are
used as the clock source, then the PLLLOCKPRD register must be written with a value of 10,000 (minimum).
Copyright © 2010–2012, Texas Instruments Incorporated Peripheral and Electrical Specifications 63
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