Datasheet

TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
www.ti.com
SPRS698D NOVEMBER 2010REVISED DECEMBER 2012
Table 2-5. Terminal Functions
(1)
(continued)
PIN NO.
PIN NAME I/O/Z DESCRIPTION
PZ PN
PZP PFP
ADC External Reference – only used when in ADC external reference mode. See
Section 5.10.1, Analog-to-Digital Converter (ADC).
V
REFHI
24 19
NOTE: V
REFHI
and ADCINA0 share the same pin on the 80-pin PN and PFP devices
and their use is mutually exclusive to one another.
ADCINB7 35 I ADC Group B, Channel 7 input
ADCINB6 34 27 I ADC Group B, Channel 6 input
COMP3B I Comparator Input 3B
AIO14 I/O Digital AIO 14
ADCINB5 33 26 I ADC Group B, Channel 5 input
ADCINB4 32 25 I ADC Group B, Channel 4 input
COMP2B I Comparator Input 2B
AIO12 I/O Digital AIO12
ADCINB3 31 I ADC Group B, Channel 3 input
ADCINB2 30 24 I ADC Group B, Channel 2 input
COMP1B I Comparator Input 1B
AIO10 I/O Digital AIO 10
ADCINB1 29 23 I ADC Group B, Channel 1 input
ADCINB0 28 22 I ADC Group B, Channel 0 input
V
REFLO
27 21 NOTE: V
REFLO
is always connected to V
SSA
on the 80-pin PN and PFP devices.
CPU AND I/O POWER
V
DDA
25 20 Analog Power Pin. Tie with a 2.2-μF capacitor (typical) close to the pin.
Analog Ground Pin.
V
SSA
26 21
NOTE: V
REFLO
is always connected to V
SSA
on the 80-pin PN and PFP devices.
V
DD
3 2
V
DD
14 12
CPU and Logic Digital Power Pins – no supply source needed when using internal
V
DD
37 29
VREG. Tie with 1.2 µF (minimum) ceramic capacitor (10% tolerance) to ground when
using internal VREG. Higher value capacitors may be used, but could impact supply-
V
DD
63 51
rail ramp-up time.
V
DD
81 65
V
DD
91 72
V
DDIO
5 4
V
DDIO
13 11
V
DDIO
38 30
Digital I/O and Flash Power Pin – Single Supply source when VREG is enabled.
V
DDIO
61 49
V
DDIO
79 63
V
DDIO
93 74
V
SS
4 3
V
SS
15 13
V
SS
36 28
V
SS
47 38 Digital Ground Pins
V
SS
62 50
V
SS
80 64
V
SS
92 73
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