Datasheet

TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
www.ti.com SPRS698D –NOVEMBER 2010–REVISED DECEMBER 2012
Table 5-65. GPIOA MUX
(1) (2)
DEFAULT AT RESET
PERIPHERAL PERIPHERAL PERIPHERAL
PRIMARY I/O
SELECTION 1 SELECTION 2 SELECTION 3
FUNCTION
GPAMUX1 REGISTER
(GPAMUX1 BITS = 00) (GPAMUX1 BITS = 01) (GPAMUX1 BITS = 10) (GPAMUX1 BITS = 11)
BITS
1-0 GPIO0 EPWM1A (O) Reserved Reserved
3-2 GPIO1 EPWM1B (O) Reserved COMP1OUT (O)
5-4 GPIO2 EPWM2A (O) Reserved Reserved
7-6 GPIO3 EPWM2B (O) SPISOMIA (I/O) COMP2OUT (O)
9-8 GPIO4 EPWM3A (O) Reserved Reserved
11-10 GPIO5 EPWM3B (O) SPISIMOA (I/O) ECAP1 (I/O)
13-12 GPIO6 EPWM4A (O) EPWMSYNCI (I) EPWMSYNCO (O)
15-14 GPIO7 EPWM4B (O) SCIRXDA (I) ECAP2 (I/O)
17-16 GPIO8 EPWM5A (O) Reserved ADCSOCAO (O)
19-18 GPIO9 EPWM5B (O) SCITXDB (O) ECAP3 (I/O)
21-20 GPIO10 EPWM6A (O) Reserved ADCSOCBO (O)
23-22 GPIO11 EPWM6B (O) SCIRXDB (I) ECAP1 (I/O)
25-24 GPIO12 TZ1 (I) SCITXDA (O) SPISIMOB (I/O)
27-26 GPIO13 TZ2 (I) Reserved SPISOMIB (I/O)
29-28 GPIO14 TZ3 (I) SCITXDB (O) SPICLKB (I/O)
31-30 GPIO15 ECAP2 (I/O) SCIRXDB (I) SPISTEB (I/O)
GPAMUX2 REGISTER
(GPAMUX2 BITS = 00) (GPAMUX2 BITS = 01) (GPAMUX2 BITS = 10) (GPAMUX2 BITS = 11)
BITS
1-0 GPIO16 SPISIMOA (I/O) Reserved TZ2 (I)
3-2 GPIO17 SPISOMIA (I/O) Reserved TZ3 (I)
5-4 GPIO18 SPICLKA (I/O) SCITXDB (O) XCLKOUT (O)
7-6 GPIO19/XCLKIN SPISTEA (I/O) SCIRXDB (I) ECAP1 (I/O)
9-8 GPIO20 EQEP1A (I) MDXA (O) COMP1OUT (O)
11-10 GPIO21 EQEP1B (I) MDRA (I) COMP2OUT (O)
13-12 GPIO22 EQEP1S (I/O) MCLKXA (I/O) SCITXDB (O)
15-14 GPIO23 EQEP1I (I/O) MFSXA (I/O) SCIRXDB (I)
17-16 GPIO24 ECAP1 (I/O) EQEP2A
(3)
(I) SPISIMOB (I/O)
19-18 GPIO25 ECAP2 (I/O) EQEP2B
(3)
(I) SPISOMIB (I/O)
21-20 GPIO26 ECAP3 (I/O) EQEP2I
(3)
(I/O) SPICLKB (I/O)
23-22 GPIO27 HRCAP2 (I) EQEP2S
(3)
(I/O) SPISTEB (I/O)
25-24 GPIO28 SCIRXDA (I) SDAA (I/OD) TZ2 (I)
27-26 GPIO29 SCITXDA (O) SCLA (I/OD) TZ3 (I)
29-28 GPIO30 CANRXA (I) EQEP2I
(3)
(I/O) EPWM7A (O)
31-30 GPIO31 CANTXA (O) EQEP2S
(3)
(I/O) EPWM8A (O)
(1) The word "Reserved" means that there is no peripheral assigned to this GPxMUX1/2 register setting. Should it be selected, the state of
the pin will be undefined and the pin may be driven. This selection is a reserved configuration for future expansion.
(2) I = Input, O = Output, OD = Open Drain
(3) The eQEP2 peripheral is not available on the 80-pin PN or PFP package.
Copyright © 2010–2012, Texas Instruments Incorporated Peripheral and Electrical Specifications 143
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