Datasheet

INTOSC1TRIM Reg
(A)
Internal
OSC 1
(10 MHz)
OSCE
CLKCTL[INTOSC1OFF]
WAKEOSC
CLKCTL[INTOSC1HALT]
INTOSC2TRIM Reg
(A)
Internal
OSC 2
(10 MHz)
OSCE
CLKCTL[INTOSC2OFF]
CLKCTL[INTOSC2HALT]
1 = Turn OSC Off
1 = Ignore HALT
1 = Turn OSC Off
1 = Ignore HALT
XCLK[XCLKINSEL]
0 = GPIO38
1 = GPIO19
GPIO19
or
GPIO38
CLKCTL[XCLKINOFF]
0
0
1
(Crystal)
OSC
XCLKIN
X1
X2
CLKCTL[XTALOSCOFF]
0 = OSC on (default on reset)
1 = Turn OSC off
0
1
0
1
OSC1CLK
OSCCLKSRC1
WDCLK
OSC2CLK
0
1
CLKCTL[WDCLKSRCSEL]
(OSC1CLK on reset)XRS
CLKCTL[OSCCLKSRCSEL]
CLKCTL[TRM2CLKPRESCALE]
CLKCTL[TMR2CLKSRCSEL]
OSCCLKSRC2
11
Prescale
/1, /2, /4,
/8, /16
00
01, 10, 11
CPUTMR2CLK
SYNC
Edge
Detect
10
01
CLKCTL[OSCCLKSRC2SEL]
SYSCLKOUT
WAKEOSC
(Oscillators enabled when this signal is high)
EXTCLK
XTAL
XCLKIN
(OSC1CLK on reset)XRS
OSCCLK
PLL
Missing-Clock-Detect Circuit
(B)
CPU-Watchdog
TMS320F28030, TMS320F28031, TMS320F28032
TMS320F28033, TMS320F28034, TMS320F28035
www.ti.com SPRS584J –APRIL 2009–REVISED OCTOBER 2013
A. Register loaded from TI OTP-based calibration function.
B. See Section 3.7.4 for details on missing clock detection.
Figure 3-9. Clock Tree
Copyright © 2009–2013, Texas Instruments Incorporated Functional Overview 49
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TMS320F28035