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WDCLK
WDCR(WDPS[2:0])
WDCLK
WDCNTR(7:0)
WDKEY(7:0)
GoodKey
1 0 1
WDCR(WDCHK[2:0])
Bad
WDCHK
Key
WDCR(WDDIS)
ClearCounter
SCSR(WDENINT)
Watchdog
Prescaler
Generate
OutputPulse
(512OSCCLKs)
8-Bit
Watchdog
Counter
CLR
WDRST
WDINT
Watchdog
55+AA
KeyDetector
XRS
Core-reset
WDRST
(A)
Internal
Pullup
TMS320F28030, TMS320F28031, TMS320F28032
TMS320F28033, TMS320F28034, TMS320F28035
SPRS584J –APRIL 2009–REVISED OCTOBER 2013 www.ti.com
A. The WDRST signal is driven low for 512 OSCCLK cycles.
Figure 3-13. CPU-watchdog Module
The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode.
In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains
functional is the CPU-watchdog. This module will run off OSCCLK. The WDINT signal is fed to the LPM
block so that it can wake the device from STANDBY (if enabled). See Section 3.8, Low-power Modes
Block, for more details.
In IDLE mode, the WDINT signal can generate an interrupt to the CPU, via the PIE, to take the CPU out of
IDLE mode.
In HALT mode, the CPU-watchdog can be used to wake up the device through a device reset.
54 Functional Overview Copyright © 2009–2013, Texas Instruments Incorporated
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