Datasheet
TMS320F28030, TMS320F28031, TMS320F28032
TMS320F28033, TMS320F28034, TMS320F28035
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SPRS584J –APRIL 2009–REVISED OCTOBER 2013
3.2.17 Peripheral Frames 0, 1, 2, 3 (PFn)
The device segregates peripherals into four sections. The mapping of peripherals is as follows:
PF0: PIE: PIE Interrupt Enable and Control Registers Plus PIE Vector Table
Flash: Flash Waitstate Registers
Timers: CPU-Timers 0, 1, 2 Registers
CSM: Code Security Module KEY Registers
ADC: ADC Result Registers
CLA Control Law Accelrator Registers and Message RAMs
PF1: GPIO: GPIO MUX Configuration and Control Registers
eCAN: Enhanced Control Area Network Configuration and Control Registers
LIN: Local Interconnect Network Configuration and Control Registers
eCAP: Enhanced Capture Module and Registers
eQEP: Enhanced Quadrature Encoder Pulse Module and Registers
HRCAP: High-Resolution Capture Module and Registers
PF2: SYS: System Control Registers
SCI: Serial Communications Interface (SCI) Control and RX/TX Registers
SPI: Serial Port Interface (SPI) Control and RX/TX Registers
ADC: ADC Status, Control, and Configuration Registers
I
2
C: Inter-Integrated Circuit Module and Registers
XINT: External Interrupt Registers
PF3: ePWM: Enhanced Pulse Width Modulator Module and Registers
HRPWM: High-Resolution Pulse-Width Modulator Registers
Comparators: Comparator Modules
3.2.18 General-Purpose Input/Output (GPIO) Multiplexer
Most of the peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. This
enables the user to use a pin as GPIO if the peripheral signal or function is not used. On reset, GPIO pins
are configured as inputs. The user can individually program each pin for GPIO mode or peripheral signal
mode. For specific inputs, the user can also select the number of input qualification cycles. This is to filter
unwanted noise glitches. The GPIO signals can also be used to bring the device out of specific low-power
modes.
Copyright © 2009–2013, Texas Instruments Incorporated Functional Overview 35
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