Datasheet

TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022
TMS320F28021, TMS320F28020, TMS320F280200
www.ti.com SPRS523J –NOVEMBER 2008–REVISED OCTOBER 2013
3.5.1 External Interrupts
Table 3-14. External Interrupt Registers
NAME ADDRESS SIZE (x16) DESCRIPTION
XINT1CR 0x00 7070 1 XINT1 configuration register
XINT2CR 0x00 7071 1 XINT2 configuration register
XINT3CR 0x00 7072 1 XINT3 configuration register
XINT1CTR 0x00 7078 1 XINT1 counter register
XINT2CTR 0x00 7079 1 XINT2 counter register
XINT3CTR 0x00 707A 1 XINT3 counter register
Each external interrupt can be enabled/disabled or qualified using positive, negative, or both positive and
negative edge. For more information, see the TMS320x2802x/TMS320F2802xx Piccolo System Control
and Interrupts Reference Guide (literature number SPRUFN3).
3.6 VREG/BOR/POR
Although the core and I/O circuitry operate on two different voltages, these devices have an on-chip
voltage regulator (VREG) to generate the V
DD
voltage from the V
DDIO
supply. This eliminates the cost and
space of a second external regulator on an application board. Additionally, internal power-on reset (POR)
and brown-out reset (BOR) circuits monitor both the V
DD
and V
DDIO
rails during power-up and run mode.
3.6.1 On-chip Voltage Regulator (VREG)
A linear regulator generates the core voltage (V
DD
) from the V
DDIO
supply. Therefore, although capacitors
are required on each V
DD
pin to stabilize the generated voltage, power need not be supplied to these pins
to operate the device. Conversely, the VREG can be disabled, should power or redundancy be the
primary concern of the application.
3.6.1.1 Using the On-chip VREG
To utilize the on-chip VREG, the VREGENZ pin should be tied low and the appropriate recommended
operating voltage should be supplied to the V
DDIO
and V
DDA
pins. In this case, the V
DD
voltage needed by
the core logic will be generated by the VREG. Each V
DD
pin requires on the order of 1.2 μF (minimum)
capacitance for proper regulation of the VREG. These capacitors should be located as close as possible
to the V
DD
pins.
3.6.1.2 Disabling the On-chip VREG
To conserve power, it is also possible to disable the on-chip VREG and supply the core logic voltage to
the V
DD
pins with a more efficient external regulator. To enable this option, the VREGENZ pin must be tied
high.
Copyright © 2008–2013, Texas Instruments Incorporated Functional Overview 37
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TMS320F28020 TMS320F280200