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Bit0 Bit(n-1) (n-2) (n-3) (n-4)
Bit0 Bit(n-1) (n-2) (n-3) (n-4)
M59
M58
M55
M57
M56
M54M53
CLKX
FSX
DX
DR
M62
TMS320DM355
Digital Media System-on-Chip (DMSoC)
SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007
Table 5-43. ASP as SPI Timing Requirements
CLKSTP = 11b, CLKXP = 1 (see Figure 5-45 )
MASTER
NO. UNIT
MIN MAX
M58 t
su(DRV-CKXL)
Setup time, DR valid before CLKX low 11 ns
M59 t
h(CKXL-DRV)
Hold time, DR valid after CLKX low 0 ns
Table 5-44. ASP as SPI Switching Characteristics
(1) (2)
CLKSTP = 11b, CLKXP = 1 (see Figure 5-45 )
MASTER
NO. PARAMETER UNIT
MIN MAX
38.5 or
M62 tc(CKX) Cycle time, CLKX ns
2P
(3) (3)
M53 t
d(CKXH-FXH)
Delay time, CLKX high to FSX high
(4)
D – 1 D + 3 ns
M54 t
d(FXL-CKXL)
Delay time, FSX low to CLKX low
(5)
T – 2 T + 2 ns
M55 t
d(CKXL-DXV)
Delay time, CLKX low to DX valid –2 6 ns
Disable time, DX high impedance following last data bit from
M56 t
dis(CKXH-DXHZ)
– 3 + 3 ns
CLKX high
M57 t
d(FXL-DXV)
Delay time, FSX low to DX valid C – 1 C + 10 ns
(1) P = (1/SYSCLK2), where SYSCLK2 is an output clock of PLLC1 (see Section 3.5 ) .
(2) T = CLKX period = (1 + CLKGDV) × P
C = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) × P when CLKGDV is even
D = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) × P when CLKGDV is even
(3) Use which ever value is greater.
(4) FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master ASP
(5) FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master
clock (CLKX).
Figure 5-45. ASP as SPI: CLKSTP = 11b, CLKXP = 1
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