Digital Media System-on-Chip (DMSoC) Product Preview

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Bit0 Bit(n-1) (n-2) (n-3) (n-4)
Bit0 Bit(n-1) (n-2) (n-3) (n-4)
M31
M30
M26M27
M25
M24
CLKX
FSX
DX
DR
M33
TMS320DM355
Digital Media System-on-Chip (DMSoC)
SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007
Table 5-37. ASP as SPI Timing Requirements
CLKSTP = 10b, CLKXP = 0 (see Figure 5-42 )
MASTER
NO. UNIT
MIN MAX
M30 t
su(DRV-CKXL)
Setup time, DR valid before CLKX low 11 ns
M31 t
h(CKXL-DRV)
Hold time, DR valid after CLKX low 0 ns
Table 5-38. ASP as SPI Switching Characteristics
(1) (2)
CLKSTP = 10b, CLKXP = 0 (see Figure 5-42 )
MASTER
NO. PARAMETER UNIT
MIN MAX
38.5 or
M33 tc(CKX) Cycle time, CLKX ns
2P
(1) (3)
M24 t
d(CKXL-FXH)
Delay time, CLKX low to FSX high
(2)
T – 2 T + 3 ns
M25 t
d(FXL-CKXH)
Delay time, FSX low to CLKX high
(4)
C – 2 C + 2 ns
M26 t
d(CKXH-DXV)
Delay time, CLKX high to DX valid –2 6 ns
M27 t
dis(CKXL-DXHZ)
Disable time, DX high impedance following last data bit from CLKX low C – 3 C +3 ns
(1) P = (1/SYSCLK2), where SYSCLK2 is an output clock of PLLC1 (see Section 3.5 ) .
(2) T = BCLKX period = (1 + CLKGDV) × 2P
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) × 2P when CLKGDV is even
(3) Use which ever value is greater.
(4) FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master
clock (CLKX).
Figure 5-42. ASP as SPI: CLKSTP = 10b, CLKXP = 0
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