Datasheet

TMP431
TMP432
www.ti.com SBOS441F –SEPTEMBER 2009–REVISED AUGUST 2013
Fault Status Register
Once all data have been transferred, the master
generates a STOP condition. STOP is indicated by
The Fault Status Register indicates if there is a fault
pulling SDA from low to high, while SCL is high.
on the remote channel diode. Bit 2 is set if remote
channel 2 is open or faultily connected. Similarly, bit 1
SERIAL INTERFACE
corresponds to remote channel 1.
The TMP431/32 operate only as slave devices on
Channel Mask Register
either the Two-Wire bus or the SMBus. Connections
to either bus are made via the open-drain I/O lines,
The Channel Mask Register controls individual
SDA and SCL. The SDA and SCL pins feature
channel masking. When a channel is masked, the
integrated spike suppression filters and Schmitt
ALERT pin is asserted when the masked channel
triggers to minimize the effects of input spikes and
reads a diode fault or out-of-limit error.
bus noise. The TMP431/32 support the transmission
protocol for fast (1kHz to 400kHz) and high-speed
High Limit Status Register
(1kHz to 3.4MHz) modes. All data bytes are
The High Limit Status Register contains the status
transmitted MSB first.
bits that are set when a temperature channel high
limit is exceeded. If any of these bits are set, then the
SERIAL BUS ADDRESS
HIGH status bit in the Status Register is set.
To communicate with the TMP431/32, the master
must first address slave devices via a slave address
Low Limit Status Register
byte. The slave address byte consists of seven
The Low Limit Status Register contains the status bits
address bits, and a direction bit that indicates the
that are set when a temperature channel low limit is
intent of executing a read or write operation.
exceeded. If any of these bits are set, then the LOW
The address of the TMP431A/32A/31C is 4Ch
status bit in the Status Register is set.
(1001100b). The address of the TMP431B/32B/31D
is 4Dh (1001101b).
THERM Limit Status Register
The THERM Limit Status Register contains the status
READ/WRITE OPERATIONS
bits that are set when a temperature channel THERM
Accessing a particular register on the TMP431/32 is
limit is exceeded. If any of these bits are set, then the
accomplished by writing the appropriate value to the
THERM status bit in the Status Register is set.
Pointer Register. The value for the Pointer Register is
the first byte transferred after the slave address byte
BUS OVERVIEW
with the R/W bit low. Every write operation to the
The TMP431/32 are SMBus interface-compatible. In
TMP431/32 require a value for the Pointer Register
SMBus protocol, the device that initiates the transfer
(see Figure 19).
is called a master, and the devices controlled by the
When reading from the TMP431/32, the last value
master are slaves. The bus must be controlled by a
stored in the Pointer Register by a write operation is
master device that generates the serial clock (SCL),
used to determine which register is read by a read
controls the bus access, and generates the START
operation. To change the register pointer for a read
and STOP conditions.
operation, a new value must be written to the Pointer
To address a specific device, a START condition is
Register. This transaction is accomplished by issuing
initiated. START is indicated by pulling the data line
a slave address byte with the R/W bit low, followed
(SDA) from a high to low logic level while SCL is
by the Pointer Register byte. No additional data are
high. All slaves on the bus shift in the slave address
required. The master can then generate a START
byte, with the last bit indicating whether a read or
condition and send the slave address byte with the
write operation is intended. During the ninth clock
R/W bit high to initiate the read command. See
pulse, the slave being addressed responds to the
Figure 20 for details of this sequence. If repeated
master by generating an Acknowledge and pulling
reads from the same register are desired, it is not
SDA low.
necessary to continually send the Pointer Register
bytes, because the TMP431/32 retain the Pointer
Data transfer is then initiated and sent over eight
Register value until it is changed by the next write
clock pulses followed by an Acknowledge bit. During
operation. Note that register bytes are sent MSB first,
data transfer SDA must remain stable while SCL is
followed by the LSB.
high, because any change in SDA while SCL is high
is interpreted as a control signal.
Copyright © 2009–2013, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Links: TMP431 TMP432