Datasheet

Frame1Two-WireSlaveAddressByte Frame2PointerRegisterByte
1
StartBy
Master
ACKBy
TMP105
ACKBy
TMP105
Frame3Two-WireSlaveAddressByte Frame4DataByte1ReadRegister
StartBy
Master
ACKBy
TMP105
ACKBy
Master
From
TMP105
1 9 1
9
1 9 1
9
SDA
SCL
0 0 R/W
0 0 0 0 0 0 P1 P0
¼
¼
¼
¼
SDA
(Continued)
SCL
(Continued)
SDA
(Continued)
SCL
(Continued)
1 0 0 1
0 0 A0
0 0 A0
R/W
D7 D6 D5 D4 D3 D2 D1 D0
Frame5DataByte2ReadRegister
StopBy
Master
ACKBy
Master
From
TMP105
1
9
D7 D6 D5 D4 D3 D2 D1 D0
Frame1SMBusALERTResponseAddressByte Frame2SlaveAddressByte
StartBy
Master
ACKBy
TMP105
From
TMP105
NACKBy
Master
StopBy
Master
1 9 1
9
SDA
SCL
ALERT
0 0 0 1 1 0 0 R/W
1 0 0 1 0 0 A0
Status
TMP105
www.ti.com SLLS648D –FEBRUARY 2005– REVISED SEPTEMBER 2011
Figure 6. Two-Wire Timing Diagram for Read Word Format
Figure 7. Timing Diagram for SMBus ALERT
Copyright © 2005–2011, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): TMP105