Datasheet

F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B

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SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014

For each of the 8 pins in set A of the Cortex-M3 GPIO registers, register GPIOPCTL selects between 1 of

11 possible primary Cortex-M3 peripheral signals, or 1 of 4 possible alternate peripheral signals. Register

GPIOAPSEL then picks one output to propagate further along the muxing chain towards a given pin. The

input takes the reverse path. See Table 3-28 and Table 3-29 for the mapping of Cortex-M3 peripheral

signals to GPIO_MUX1 pins.

Similarly, on the C28x side, GPAMUX1 and GPAMUX2 registers select 1 of 4 possible C28x peripheral

signals for each of 32 pins of set A. The selected C28x peripheral output then propagates further along

the muxing chain towards a given pin. The input takes the reverse path. See Table 3-30 for the mapping

of C28x peripheral signals to GPIO_MUX1 pins.

In addition to passing mostly digital signals, four GPIO_MUX1 pins can also be assigned to analog

signals. The GPIO Analog Mode Select (GPIOAMSEL) Register is used to assign four pins to analog USB

signals. PF6_GPIO38 becomes USB0VBUS, PG2_GPIO42 becomes USB0DM, PG5_GPIO45 becomes

USB0DP, and PG6_GPIO46 becomes USB0ID. When analog mode is selected, these four pins are not

available for digital GPIO_MUX1 options as described above.

Another special case is the External Oscillator Input signal (XCLKIN). This signal, available through pin

PJ7_GPIO63, is directly tied to USBPLLCLK (clock input to USB PLL) and two CAN modules. XCLKIN is

always available at these modules where it can be selected through local registers.

NOTE

For GPIO_MUX1 pins PF6_GPIO38 and PG6_GPIO46, only the corresponding USB function

is available on silicon revision 0 devices (GPIO and other functions listed in Table 4-1 are not

available).

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