Datasheet

INTERNAL
OSC
MAIN
PLL
X1
PIN
MISSING
CLK DETECT
CLOCKFAIL
MAIN
OSC
10MHZCLK
PLLSYSCLK
OSCCLK
EPWM
M3 NMI
C28x NMI
M3
CPU
C28x
CPU
M3 NMI WDOG
C28x NMI WDOG
RESETS
ADDITIONAL CLOCK CONTROL LOGIC
GPIO_MUX1
1
1
2
4
5
5
6
7
7
2
3
5
6
7
THE INPUT CLOCK IS DISRUPTED
CLOCKFAIL SIGNAL BECOMES ACTIVE
PLLSYSCLK SWITCHES TO THE 10MHZCLK
CPUS RESPOND TO NMIS AND THE
WATCHDOGS START COUNTING
3
3
SOFTWARE TAKES CORRECTIVE/RECOVERY ACTION
IF SOFTWARE DOES NOT STOP THE WATCHDOG COUNTERS, THE
WATCHDOGS WILL RESET THE DEVICE AFTER THE COUNT RUNS OUT
TYPICAL ACTIVITY FOLLOWING
A MISSING CLOCK DETECTION :
4
CLOCK FAIL SIGNAL IS SENT TO M3 NMI BLOCK, C28 NMI
BLOCK, EPWM MODULES AND THE PLLSYSCLK MUX
3
M3SSCLK
C28CLKIN
3
X2
PIN
EPWM_A EPWM_B
OTHER NMI
SOURCES
CLOCKFAIL
CLOCKFAIL
C28CLKIN
M3NMI
C28NMI
PIN PIN
F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B
SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014 www.ti.com
Figure 3-13. Missing Clock Detection
64 Device Overview Copyright © 2012–2014, Texas Instruments Incorporated
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Product Folder Links: F28M36P63C F28M36P53C F28M36H53C F28M36H53B F28M36H33C F28M36H33B