Datasheet

MAIN
OSC
INTEGER
MULTIPLIER
FRACTIONAL
MULTIPLIER
PIN
X1
SYSPLLMULT REG
/2
MAIN PLL
0000000 : x 1
0000001 : x 1
0000010 : x 2
0000011 : x 3
.
.
.
1111101: x 125
1111110: x 126
1111111: x 127
EXAMPLE 1: X1 = 100 MHZ SPLLIMULT = 0000000 ( BYPASS PLL) N/A PLLSYSCLK = 100 MHz
EXAMPLE 2: X1 = 10 MHz SPLLIMULT = 0010100 ( x 20 ) SPLLFM ULT = 00 ( NOT USED) PLLSYSCLK = [ ( 10 x 20) / 2 ] / 1 = 100 MHz
EXAMPLE 3: X1 = 10 MHz SPLLIMULT = 0010100 ( x 20 ) SPLLFM ULT = 10 ( x 0.50) PLLSYSCLK = [ ( 10 x 20.5) / 2 ] / 1 = 102.5 MHz
SPLLIMULT SPLLFMULT
0
1
PLLSYSCLK
OUPUT OF
MAIN PLL
IS ALWAYS
DIVIDED BY 2
00: NOT USED
01: x 0.25
10: x 0.50
11: x 0.75
7 2
OSCCLK
OSCCLK
SYSDIVSEL REG
/1
/2
/4
/8
SYSDIVSEL (1:0)
= 00 ( /1 )
(1) OUTPUT OF THE MAIN PLL MUST RANGE BETWEEN 150 550 MHz.–
SYSPLLCTL REG
SPLLEN
(2)
SPLLCLKEN
(2) WHEN SPLLEN BIT = 0, THE MAIN PLL IS POWERED OFF.
F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B
www.ti.com SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014
Figure 3-8. Main PLL
Copyright © 2012–2014, Texas Instruments Incorporated Device Overview 47
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