Datasheet

20
15
SPISIMO
SPISOMI
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
SPISIMO Data
Must Be Valid
SPISOMI Data Is Valid
19
16
14
13
12
SPISTE
(A)
F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B
SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014 www.ti.com
A. In the slave mode, the SPISTE signal should be asserted low at least 0.5t
c(SPC)
(minimum) before the valid SPI clock
edge and remain low for at least 0.5t
c(SPC)
after the receiving edge (SPICLK) of the last data bit.
Figure 7-44. SPI Slave Mode External Timing (Clock Phase = 0)
234 Peripheral Information and Timings Copyright © 2012–2014, Texas Instruments Incorporated
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