Datasheet
F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B
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SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014
Table 7-41. SPI Master Mode External Timing (Clock Phase = 1)
(1) (2) (3) (4) (5)
SPI WHEN (SPIBRR + 1) IS EVEN OR SPI WHEN (SPIBRR + 1) IS ODD
SPIBRR = 0 OR 2 AND SPIBRR > 3
NO. UNIT
MIN MAX MIN MAX
1 t
c(SPC)M
Cycle time, SPICLK 4t
c(LCO)
128t
c(LCO)
5t
c(LCO)
127t
c(LCO)
ns
2 t
w(SPCH)M
Pulse duration, SPICLK high 0.5t
c(SPC)M
– 10 0.5t
c(SPC)M
0.5t
c(SPC)M
– 0.5t
c(LCO)
– 10 0.5t
c(SPC)M
– 0.5t
c(LCO)
ns
(clock polarity = 0)
t
w(SPCL))M
Pulse duration, SPICLK low 0.5t
c(SPC)M
– 10 0.5t
c(SPC)M
0.5t
c(SPC)M
– 0.5t
c(LCO)
– 10 0.5t
c(SPC)M
– 0.5t
c(LCO)
(clock polarity = 1)
3 t
w(SPCL)M
Pulse duration, SPICLK low 0.5t
c(SPC)M
– 10 0.5t
c(SPC)M
0.5t
c(SPC)M
+ 0.5t
c(LCO)
– 10 0.5t
c(SPC)M
+ 0.5t
c(LCO)
ns
(clock polarity = 0)
t
w(SPCH)M
Pulse duration, SPICLK high 0.5t
c(SPC)M
– 10 0.5t
c(SPC)M
0.5
tc(SPC)M
+ 0.5t
c(LCO)
– 10 0.5t
c(SPC)M
+ 0.5t
c(LCO)
(clock polarity = 1)
6 t
su(SIMO-SPCH)M
Setup time, SPISIMO data valid before 0.5t
c(SPC)M
– 10 0.5t
c(SPC)M
– 10 ns
SPICLK high (clock polarity = 0)
t
su(SIMO-SPCL)M
Setup time, SPISIMO data valid before 0.5t
c(SPC)M
– 10 0.5t
c(SPC)M
– 10
SPICLK low (clock polarity = 1)
7 t
v(SPCH-SIMO)M
Valid time, SPISIMO data valid after 0.5t
c(SPC)M
– 10 0.5t
c(SPC)M
– 10 ns
SPICLK high (clock polarity = 0)
t
v(SPCL-SIMO)M
Valid time, SPISIMO data valid after 0.5t
c(SPC)M
– 10 0.5t
c(SPC)M
– 10
SPICLK low (clock polarity = 1)
10 t
su(SOMI-SPCH)M
Setup time, SPISOMI before SPICLK high 35 35 ns
(clock polarity = 0)
t
su(SOMI-SPCL)M
Setup time, SPISOMI before SPICLK low 35 35
(clock polarity = 1)
11 t
v(SPCH-SOMI)M
Valid time, SPISOMI data valid after 0.25t
c(SPC)M
– 10 0.5t
c(SPC)M
– 10 ns
SPICLK high (clock polarity = 0)
t
v(SPCL-SOMI)M
Valid time, SPISOMI data valid after 0.25
tc(SPC)M
– 10 0.5
tc(SPC)M
– 10
SPICLK low (clock polarity = 1)
(1) The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.
(2) t
c(SPC)
= SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5 MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5 MHz MAX.
(4) t
c(LCO)
= LSPCLK cycle time
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
Copyright © 2012–2014, Texas Instruments Incorporated Peripheral Information and Timings 231
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