Datasheet

1
2
MIIRXCK
MIIRXD[3:0],
MIIRXDV,
MIIRXER (Inputs)
1
MIITXCK
MIITXD[3:0],
MIITXEN
F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B
www.ti.com SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014
Table 7-26. Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise
Noted) for EMAC MII Transmit (see Figure 7-29)
NO. PARAMETER MIN MAX UNIT
1 t
d(TXCKH-MTXDV)
Delay time, MIITXCK high to transmit selected signals valid 5 25 ns
Figure 7-29. 100/10Mb/s MII Transmit Timing
Table 7-27. Timing Requirements for EMAC MII Receive (see Figure 7-30)
NO. MIN NOM MAX UNIT
1 t
su(MRXDV-RXCKH)
Setup time, receive selected signals valid before MIIRXCK high 8 ns
2 t
h(RXCKH-MRXDV)
Hold time, receive selected signals valid after MIIRXCK high 7 ns
Figure 7-30. 100/10Mb/s MII Receive Timing
Copyright © 2012–2014, Texas Instruments Incorporated Peripheral Information and Timings 209
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