Datasheet
F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B
www.ti.com
SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014
7.1.4.3.2.3 HB-16 FIFO Mode
The HB-16 FIFO Mode uses 16 bits of data, removes ALE and address pins, and optionally adds external
FIFO Full/Empty flag inputs. This scheme is used by many devices, such as radios, communication
devices (including USB2 devices), and some FPGA configuration (FIFO throughblock RAM). This FIFO
Mode presents the data side of the normal Host-Bus interface, but is paced by FIFO control signals. It is
important to consider that the FIFO Full/Empty control inputs may stall the EPI interface and can
potentially block other CPU or DMA accesses. For detailed maps of the HB-16 FIFO Mode, see Table 7-
15.
Table 7-15. EPI MODES – 16-Bit Host-Bus Mode (EPICFG/MODE = 0x3),
FIFO Mode (EPIHB16CFG/MODE = 0x3)
EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN
With One With Two
Accessible by (Available GPIOMUX_1
Accessible by C28x Chip Select Chip Selects
Cortex-M3 Muxing Choices for EPI)
(CSCFG = 0x1) (CSCFG = 0x2)
EPI0S0 D0 D0 PH3_GPIO51
EPI0S1 D1 D1 PH2_GPIO50
EPI0S2 D2 D2 PC4_GPIO68
EPI0S3 D3 D3 PC5_GPIO69
EPI0S4 D4 D4 PC6_GPIO70
EPI0S5 D5 D5 PC7_GPIO71
EPI0S6 D6 D6 PH0_GPIO48
EPI0S7 D7 D7 PH1_GPIO49
EPI0S8 D8 D8 PE0_GPIO24
EPI0S9 D9 D9 PE1_GPIO25
EPI0S10 D10 D10 PH4_GPIO52
EPI0S11 D11 D11 PH5_GPIO53
EPI0S12 D12 D12 PF4_GPIO36
EPI0S13 D13 D13 PG0_GPIO40
EPI0S14 D14 D14 PG1_GPIO41
EPI0S15 D15 D15 PF5_GPIO37
EPI0S25 x CS1 PE3_GPIO27
EPI0S30 CS0 CS0 PD7_GPIO23 PJ6_GPIO62
EPI0S27 FFULL FFULL PH7_GPIO55
EPI0S26 FEMPTY FEMPTY PH6_GPIO54
EPI0S29 WR WR PD6_GPIO22 PJ5_GPIO61
EPI0S28 RD RD PD5_GPIO21 PJ4_GPIO60
EPI0S32 x x PF2_GPIO34 PC0_GPIO64
EPI0S16 x x PJ0_GPIO56
EPI0S17 x x PJ1_GPIO57
EPI0S18 x x PJ2_GPIO58
EPI0S19 x x PD4_GPIO20 PJ3_GPIO59
EPI0S20 x x PD2_GPIO18
EPI0S21 x x PD3_GPIO19
EPI0S22 x x PB5_GPIO13
EPI0S23 x x PB4_GPIO12
EPI0S24 x x PE2_GPIO26
EPI0S31 x x PG7_GPIO47
Copyright © 2012–2014, Texas Instruments Incorporated Peripheral Information and Timings 183
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