Datasheet

F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B
SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014 www.ti.com
7.1.4.3.1.2 HB-8 Non-Muxed Address/Data Mode
The HB-8 Non-Muxed Mode uses dedicated pins for address and data signals. For this reason, the Non-
Muxed Mode has reduced address reach as compared to the Muxed Mode. The HB-8 Non-Muxed Mode
is selected with the MODE field of the HB-8 Configuration Register. In addition to data and address
signals, the HB-8 Non-Muxed Mode also features the ALE signal (indicating to an external latch to capture
address and hold the address until the data phase); RD and WR data strobes; and 1–4 CS (chip select)
signals to enable one of four external peripherals. The ALE and CS options are chosen with the CSCFG
field of the HB-8 Configuration2 Register. For more detailed maps of the HB-8 Non-Muxed Mode, see
Table 7-7.
Table 7-7. EPI MODES – 8-Bit Host-Bus Mode (EPICFG/MODE = 0x2),
Non-Muxed (EPIHB16CFG/MODE = 0x1)
EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN
With With With With
Accessible by Accessible by Address Latch One Two ALE and Two (Available GPIOMUX_1
Cortex-M3 C28x Enable Chip Select Chip Selects Chip Selects Muxing Choices for EPI)
(CSCFG = 0x0) (CSCFG = 0x1) (CSCFG = 0x2) (CSCFG = 0x3)
EPI0S0 D0 D0 D0 D0 PH3_GPIO51
EPI0S1 D1 D1 D1 D1 PH2_GPIO50
EPI0S2 D2 D2 D2 D2 PC4_GPIO68
EPI0S3 D3 D3 D3 D3 PC5_GPIO69
EPI0S4 D4 D4 D4 D4 PC6_GPIO70
EPI0S5 D5 D5 D5 D5 PC7_GPIO71
EPI0S6 D6 D6 D6 D6 PH0_GPIO48
EPI0S7 D7 D7 D7 D7 PH1_GPIO49
EPI0S8 A0 A0 A0 A0 PE0_GPIO24
EPI0S9 A1 A1 A1 A1 PE1_GPIO25
EPI0S10 A2 A2 A2 A2 PH4_GPIO52
EPI0S11 A3 A3 A3 A3 PH5_GPIO53
EPI0S12 A4 A4 A4 A4 PF4_GPIO36
EPI0S13 A5 A5 A5 A5 PG0_GPIO40
EPI0S14 A6 A6 A6 A6 PG1_GPIO41
EPI0S15 A7 A7 A7 A7 PF5_GPIO37
EPI0S16 A8 A8 A8 A8 PJ0_GPIO56
EPI0S17 A9 A9 A9 A9 PJ1_GPIO57
EPI0S18 A10 A10 A10 A10 PJ2_GPIO58
EPI0S19 A11 A11 A11 A11 PD4_GPIO20 PJ3_GPIO59
EPI0S20 A12 A12 A12 A12 PD2_GPIO18
EPI0S21 A13 A13 A13 A13 PD3_GPIO19
EPI0S22 A14 A14 A14 A14 PB5_GPIO13
EPI0S23 A15 A15 A15 A15 PB4_GPIO12
EPI0S24 A16 A16 A16 A16 PE2_GPIO26
EPI0S25 A17 A17 A17 A17 PE3_GPIO27
EPI0S26 A18 A18 A18 CS0 PH6_GPIO54
EPI0S27 A19 A19 CS1 CS1 PH7_GPIO55
EPI0S30 ALE CS0 CS0 ALE PD7_GPIO23 PJ6_GPIO62
EPI0S29 WR WR WR WR PD6_GPIO22 PJ5_GPIO61
EPI0S28 RD RD RD RD PD5_GPIO21 PJ4_GPIO60
EPI0S31 x x x x PG7_GPIO47
EPI0S32 x x x x PF2_GPIO34 PC0_GPIO64
EPI0S33 x x x x PF3_GPIO35 PC1_GPIO65
172 Peripheral Information and Timings Copyright © 2012–2014, Texas Instruments Incorporated
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