Datasheet

ADCSOCAO

ADCSOCBO

w(ADCSOCL)

-40 -35 -30 -25 -20 -15 -10 -5 10 15 20 25 30 35 40

Temperature (°C)

Typical ADC Total Error

Total Error (LSBs)

45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 1250 5

F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B

SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014

www.ti.com

A. Gain error contribution is based on sampling of full-scale voltage using internal reference mode.

B. Periodic ADC offset re-cal is assumed.

C. Total error shown represents the absolute value of possible error.

Figure 7-2. Typical ADC Total Error

[Temperature (°C) versus Total Error (LSBs)]

Table 7-2. External ADC Start-of-Conversion Switching Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER MIN MAX UNIT

w(ADCSOCL)

Pulse duration, ADCSOCxO low 32t

c(HCO)

cycles

Figure 7-3. ADCSOCAO or ADCSOCBO Timing

7.1.2 Comparator + DAC Units

Figure 7-4 shows the internal structure of the six analog Comparator + DAC units present in Concerto

devices. Each unit compares two analog inputs (A and B) and assigns a value of ‘1’ when the voltage of

the A input is greater than that of the B input, or a value of ‘0’ when the opposite is true. The six A inputs

and six B inputs come from AIO_MUX1 and AIO_MUX2. All six B inputs can also be provided by the 10-

bit digital-to-analog units that are present in each comparator DAC. The 10-bit value for each DAC unit is

programmed in the respective DACVAL register. Another comparator register, COMPCTL, can be

programmed to select the source of the B input, to enable or disable the comparator circuit, to invert

comparator output, to synchronize comparator output to C28x SYSCLK, and to select the qualification

period (number of clock cycles). All six output signals from the six comparators can be routed out to the

device pins via GPIO_MUX2 pin mux.

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Product Folder Links: F28M36P63C F28M36P53C F28M36H53C F28M36H53B F28M36H33C F28M36H33B