Datasheet

F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B
www.ti.com SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014
Table 6-38. HALT Mode Timing Requirements
MIN MAX UNIT
t
w(WAKE-GPIO)
Pulse duration, GPIO wake-up signal t
oscst
+ 2t
c(OSCCLK)
(1)
cycles
t
w(WAKE-XRS)
Pulse duration, XRS wakeup signal t
oscst
+ 8t
c(OSCCLK)
cycles
(1) See Table 6-14 for an explanation of t
oscst
.
Table 6-39. HALT Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER MIN MAX UNIT
t
d(IDLE-XCOL)
Delay time, IDLE instruction executed to XCLKOUT low 32t
c(SCO)
45t
c(SCO)
cycles
t
p
PLL lock-up time 131072t
c(OSCCLK)
cycles
Delay time, PLL lock to program execution resume
1125t
c(SCO)
cycles
• Wake up from flash
t
d(WAKE-HALT)
– Flash module in sleep state
35t
c(SCO)
cycles
• Wake up from SARAM
Copyright © 2012–2014, Texas Instruments Incorporated Electrical Specifications 151
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