Datasheet

V
ID+
20%
V
ID
3.3V
2.8V
V
ID(pp)
V
OD(pp)
V
ID–
V
OD
20%
80% 80%
0V
t
PHL
t
PLH
t
f
t
r
T0391-01
50%
V
OL
t
sk(D)
V
Y
V
Z
V
OH
V
OC
DV
OC(SS)
T0392-01
T0424-01
t
clk1
t
clk2
V
CD(PP)
V
OD(PP)
TMDSoutputs
HiZduringthisduration
ValidInput TMDS clock
thatmeetsthemin
Frequency Thresholdand
Amplitude
TMDSoutputclockwith
peaktopeakswing
complianttotheHDMI
specandsamefrequency
astheInput TMDSclock
frequency
TMDS
outputs
HiZ
TMDS361B
www.ti.com SLLS988A –SEPTEMBER 2009– REVISED JULY 2011
Figure 10. TMDS Main-Link Timing Measurements
Figure 11. Definition of Intra-Pair Differential Skew
Figure 12. TMDS Main-Link Common-Mode Measurements
Figure 13. Clock-Detect Timing Diagram
Copyright © 2009–2011, Texas Instruments Incorporated 17