Datasheet
SLAS235B − JULY 1999 − REVISED APRIL 2004
6
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digital input timing requirements
MIN NOM MAX UNIT
t
su(CS−FS)
Setup time, CS low before FS falling edge 10 ns
t
su(FS-CK)
Setup time, FS low before first negative SCLK edge 8 ns
t
su(C16-FS)
Setup time, 16
th
negative SCLK edge after FS low on which bit D0 is sampled before rising
edge of FS
10 ns
t
su(C16-CS)
Setup time, 16
th
positive SCLK edge (first positive after D0 is sampled) before CS rising
edge. If FS is used instead of 16
th
positive edge to update DAC, then setup time between
FS rising edge and CS rising edge.
10 ns
t
wH
SCLK pulse duration high 25 ns
t
wL
SCLK pulse duration low 25 ns
t
su(D)
Setup time, data ready before SCLK falling edge 8 ns
t
H(D)
Hold time, data held valid after SCLK falling edge 5 ns
t
wH(FS)
FS pulse duration high 25 ns
PARAMETER MEASUREMENT INFORMATION
t
wL
SCLK
CS
DIN
FS
D15 D14 D13 D12 D1 D0 XX
1
X
2 3 4 5 15 16
X
t
wH
t
su(D)
t
h(D)
t
su(CS-FS)
t
wH(FS)
t
su(FS-CK)
t
su(C16-FS)
t
su(C16-CS)
Figure 1. Timing Diagram