Datasheet
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OVERVIEW
HARDWARE RESET
DIGITAL CONTROL SERIAL INTERFACE
TLV320AIC34
SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007
The TLV320AIC34 is a highly flexible, low-power, four-channel audio codec with extensive feature integration,
intended for applications in smart phones, portable computing, communication, and entertainment applications.
Available in a 6-mm × 6-mm, 87-ball BGA, the device integrates a host of features to reduce cost, board space,
and power consumption in space-constrained, battery-powered, portable applications.
The TLV320AIC34 consists of the following blocks:
• Four-channel audio multibit delta-sigma DAC (8 kHz – 96 kHz)
• Four-channel audio multibit delta-sigma ADC (8 kHz – 96 kHz)
• Dedicated programmable-gain amplifier at each ADC input, with independently configurable hardware
automatic gain control on all channels
• Programmable digital audio effects processing for record (wind noise, microphone EQ, resonance noise
removal)
• Programmable digital audio effects processing for playback (3-D, bass, treble, midrange, EQ, de-emphasis)
• Twelve audio inputs configurable for up to eight fully differential inputs or up to twelve single-ended inputs
• Eight high-power audio output drivers (headphone, and speaker drive capability for codec block A)
• Six line output drivers with fully differential or single-ended outputs
• Dual fully programmable PLLs
• Dual audio serial data busses support I
2
S, left/right-justified, DSP, PCM, and TDM operation
• Support for simultaneous, fully asynchronous operation of data converters using both serial busses
• Headphone/headset jack detection with interrupt
Control communication with the TLV320AIC34 is accomplished using the I
2
C interface, which supports both
standard and fast communication modes.
The TLV320AIC34 requires a hardware reset after power up for proper operation. After all power supplies are at
their specified values, the RESET_A and RESET_B terminals must be driven low for at least 10 ns. If this reset
sequence is not performed, the device may not respond properly to register reads/writes. It is recommended that
the two RESET_x terminals be shorted and controlled together.
The TLV320AIC34 is entirely controlled by registers, with a register map that is software compatible with the
low-power stereo audio codecs TLV320AIC31/32/33 and TLV320AIC3101/4/5/6. In order to maintain best
software compatibility with stereo codecs, the register configuration of the four-channel TLV320AIC34 is divided
into two separate I
2
C slave devices containing separate addresses, with each address used to access registers
controlling two channels of codec and associated inputs and outputs. The two partitions of the device are
denoted A and B, with analog and digital inputs, outputs, and internal blocks named accordingly, ending in _A or
_B. The two I
2
C addresses are also denoted A and B, with each used to control the correspondingly named
signals and internal blocks.
Within each I
2
C address, the register map consists of multiple pages of registers, with each page containing up
to 128 registers. The register at address zero on each page is used as a page control register, and writing to this
register determines the active page for the device. All subsequent read/write operations access the page that is
active at the time, unless a register write is performed to change the active page. Only two pages of registers
(zero and one) are implemented in this product, with the active page defaulting to page 0 on device reset.
For example, at device reset, the active page defaults to page 0, and thus all register read/write operations for
addresses 1 to 127 access registers in page 0. If registers on page 1 must be accessed, the user must write the
8-bit value 0x01 to register 0, the page control register, to change the active page from page 0 to page 1. After
this write, it is recommended that the user also read back the page control register to ensure the change in page
control has occurred properly. Future read/write operations to addresses 1 to 127 now access registers in
page 1. When page-0 registers must be accessed again, the user writes the 8-bit value 0x00 to register 0, the
page control register, to change the active page back to page 0. After a recommended read of the page control
register, all further read/write operations to addresses 1 to 127 again access page-0 registers.
22 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated
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