Datasheet
STEREO AUDIO ADC
TLV320AIC33
SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008 ...........................................................................................................................................
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The table below lists several example cases of typical MCLK rates and how to program the PLL to achieve
Fsref = 44.1 kHz or 48 kHz.
Fsref = 44.1 kHz
MCLK (MHz) P R J D ACHIEVED FSREF % ERROR
2.8224 1 1 32 0 44100.00 0.0000
5.6448 1 1 16 0 44100.00 0.0000
12.0 1 1 7 5264 44100.00 0.0000
13.0 1 1 6 9474 44099.71 0.0007
16.0 1 1 5 6448 44100.00 0.0000
19.2 1 1 4 7040 44100.00 0.0000
19.68 1 1 4 5893 44100.30 – 0.0007
48.0 4 1 7 5264 44100.00 0.0000
Fsref = 48 kHz
MCLK (MHz) P R J D ACHIEVED FSREF % ERROR
2.048 1 1 48 0 48000.00 0.0000
3.072 1 1 32 0 48000.00 0.0000
4.096 1 1 24 0 48000.00 0.0000
6.144 1 1 16 0 48000.00 0.0000
8.192 1 1 12 0 48000.00 0.0000
12.0 1 1 8 1920 48000.00 0.0000
13.0 1 1 7 5618 47999.71 0.0006
16.0 1 1 6 1440 48000.00 0.0000
19.2 1 1 5 1200 48000.00 0.0000
19.68 1 1 4 9951 47999.79 0.0004
48.0 4 1 8 1920 48000.00 0.0000
The AIC33 can also output a separate clock on the GPIO1 pin. If the PLL is being used for the audio data
converter clock, the M and N settings can be used to provide a divided version of the PLL output. If the PLL is
not being used for the audio data converter clock, the PLL can still be enabled to provide a completely
independent clock output on GPIO1. The formula for the GPIO1 clock output when PLL is enabled and
CLKMUX_OUT is 0 is:
GPIO1 = (PLLCLK_IN × 2 × K × R) / (M × N × P)
When CLKMUX_OUT is 1, regardless of whether PLL is enabled or disabled, the input to the clock output divider
can be selected as MCLK, BCLK, or GPIO2. Is this case, the formula for the GPIO1 clock is:
GPIO1 = (CLKDIV_IN × 2) / (M × N), where
M = 1, 2, 4, 8
N = 2, 3, … , 17
CLKDIV_IN can be BCLK, MCLK, or GPIO2, selected by page 0, register 102, bits D7-D6
The TLV320AIC33 includes a stereo audio ADC, which uses a delta-sigma modulator with 128-times
oversampling in single-rate mode, followed by a digital decimation filter. The ADC supports sampling rates from 8
kHz to 48 kHz in single-rate mode, and up to 96 kHz in dual-rate mode. Whenever the ADC or DAC is in
operation, the device requires an audio master clock be provided and appropriate audio clock generation be
setup within the part.
In order to provide optimal system power dissipation, the stereo ADC can be powered one channel at a time, to
support the case where only mono record capability is required. In addition, both channels can be fully powered
or entirely powered down.
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