Datasheet

WCLK
BCLK
DOUT
DIN
t
H(BCLK)
t
h(ws)
t
L(BCLK)
t
s(ws)
t
h(ws)
t
d(DO-BCLK)
t
h(ws)
t
s(DI)
t
h(DI)
WCLK
BCLK
DOUT
DIN
t
d(WS)
t
d(WS)
t
d(DO-BCLK)
t
s(DI)
t
h(DI)
TLV320AIC3204
www.ti.com SLOS602B –SEPTEMBER 2008–REVISED OCTOBER 2012
Typical DSP Timing Characteristics
All specifications at 25°C, DVdd = 1.8V
Figure 5. DSP Timing in Master Mode
Table 4. DSP Timing in Master Mode (see Figure 5)
PARAMETER IOVDD=1.8V IOVDD=3.3V UNITS
MIN MAX MIN MAX
t
d(WS)
WCLK delay 30 20 ns
t
d(DO-BCLK)
BCLK to DOUT delay 22 20 ns
t
s(DI)
DIN setup 8 8 ns
t
h(DI)
DIN hold 8 8 ns
t
r
Rise time 24 12 ns
t
f
Fall time 24 12 ns
Figure 6. DSP Timing in Slave Mode
Table 5. DSP Timing in Slave Mode (see Figure 6)
PARAMETER IOVDD=1.8V IOVDD=3.3V UNITS
MIN MAX MIN MAX
t
H(BCLK)
BCLK high period 35 35 ns
t
L(BCLK)
BCLK low period 35 35 ns
t
s(WS)
WCLK setup 8 8 ns
t
h(WS)
WCLK hold 8 8 ns
t
d(DO-BCLK)
BCLK to DOUT delay 22 22 ns
t
s(DI)
DIN setup 8 8 ns
t
h(DI)
DIN hold 8 8 ns
t
r
Rise time 4 4 ns
t
f
Fall time 4 4 ns
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